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公开(公告)号：US11764822B2
公开(公告)日：2023-09-19
申请号：US17305999
申请日：2021-07-19
Applicant: Analog Devices, Inc.
Inventor： Christopher Mayer , Manish J. Manglani
IPC: H04B1/40
CPC classification number: H04B1/40
Abstract: Radio transceiver control interfaces are provided herein. In certain embodiments, a semiconductor die includes a group of transmitters and a group of receivers that operate as a transceiver. Additionally, a group of common pins are used to control settings of both the transmitters and receivers. In one example, data received on the common pins can be used to establish enable settings for each of the transmitters and receivers. Thus, rather than using a one-to-one correspondence between a pin and the setting of a particular transmitter or receiver, a mapping is used between the common pins and the settings of the transmitters and receivers.
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公开(公告)号：US11539384B2
公开(公告)日：2022-12-27
申请号：US17382910
申请日：2021-07-22
Applicant: Analog Devices, Inc.
Inventor： Robert D. Solanki , Christopher Mayer
IPC: H04B1/04
Abstract: A transmitter with a DC detection circuit that can control when a modulator of the transmitter is active. When data is being transmitted, a tone introduced by a mixer in the transmit path is hidden by the data signal and has minimal effect on the transmit path. However, when there is no data, the tone can cause undesirable noise. A modulator may move the tone or noise outside of the transmitter's bandwidth. As the data can hide the tone, the DSM may only be needed when there is a DC signal. By activating the DSM only when a DC signal is detected, the extra power introduced by the modulator can be reduced while eliminating in-band noise.
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公开(公告)号：US20220374389A1
公开(公告)日：2022-11-24
申请号：US17817811
申请日：2022-08-05
Applicant: Analog Devices, Inc.
Inventor： Manish J. Manglani , Shipra Bhal , Christopher Mayer
Abstract: This disclosure relates to a distributed processing system for configuring multiple processing channels. The distributed processing system includes a main processor, such as an ARM processor, communicatively coupled to a plurality of co-processors, such as stream processors. The co-processors can execute instructions in parallel with each other and interrupt the ARM processor. Longer latency instructions can be executed by the main processor and lower latency instructions can be executed by the co-processors. There are several ways that a stream can be triggered in the distributed processing system. In an embodiment, the distributed processing system is a stream processor system that includes an ARM processor and stream processors configured to access different register sets. The stream processors can include a main stream processor and stream processors in respective transmit and receive channels. The stream processor system can be implemented in a radio system to configure the radio for operation.
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公开(公告)号：US20190303348A1
公开(公告)日：2019-10-03
申请号：US16103711
申请日：2018-08-14
Applicant: Analog Devices, Inc.
Inventor： Manish J. Manglani , Shipra Bhal , Christopher Mayer
Abstract: This disclosure relates to a distributed processing system for configuring multiple processing channels. The distributed processing system includes a main processor, such as an ARM processor, communicatively coupled to a plurality of co-processors, such as stream processors. The co-processors can execute instructions in parallel with each other and interrupt the ARM processor. Longer latency instructions can be executed by the main processor and lower latency instructions can be executed by the co-processors. There are several ways that a stream can be triggered in the distributed processing system. In an embodiment, the distributed processing system is a stream processor system that includes an ARM processor and stream processors configured to access different register sets. The stream processors can include a main stream processor and stream processors in respective transmit and receive channels. The stream processor system can be implemented in a radio system to configure the radio for operation.
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公开(公告)号：US20180294817A1
公开(公告)日：2018-10-11
申请号：US15957766
申请日：2018-04-19
Applicant: Analog Devices, Inc.
Inventor： Christopher Mayer , David J. McLaurin , Christopher W. Angell , Sudhir Desai , Steven R. Bal
Abstract: Apparatus and methods for phase synchronization of phase-locked loops (PLLs) are provided. In certain configurations, an RF communication system includes a PLL that generates one or more output clock signals and a phase synchronization circuit that synchronizes a phase of the PLL. The phase synchronization circuit includes a sampling circuit that generates samples by sampling the one or more output clock signals based on timing of a reference clock signal. Additionally, the phase synchronization circuit includes a phase difference calculation circuit that generates a phase difference signal based on the samples and a tracking digital phase signal representing the phase of the PLL. The phase synchronization circuit further includes a phase adjustment control circuit that provides a phase adjustment to the PLL based on the phase difference signal so as to synchronize the PLL.
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Patent Agency Ranking
公开(公告)号：US20250036587A1
公开(公告)日：2025-01-30
申请号：US18780879
申请日：2024-07-23
Applicant: Analog Devices, Inc.
Inventor： Christopher Mayer , Sudhir Desai , Arash Azizimazreah
IPC: G06F13/36
Abstract: Apparatus and methods for facilitating data movement among circuit blocks are disclosed. In certain embodiments, an integrated circuit (IC) includes a network of dataflow gaskets including a first dataflow gasket coupled to a first circuit block and a second dataflow gasket coupled to a second circuit block. The first circuit block can write to the second circuit block by programming output stream registers of the first dataflow gasket for an outgoing write stream that includes a header identifying the second dataflow gasket. The header can be provided by the first dataflow gasket to the second dataflow gasket over the network, and in response to the header reaching the second dataflow gasket, the second dataflow gasket can program the input stream registers of the second dataflow gasket for an incoming read stream.
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7.发明授权公开(公告)号：US12040753B2
公开(公告)日：2024-07-16
申请号：US17948482
申请日：2022-09-20
Applicant: Analog Devices, Inc.
Inventor： Tao Yu , Christopher Mayer
CPC classification number: H03F1/3247 , G05B13/027
Abstract: Systems, devices, and methods related to envelope regulated, digital predistortion (DPD) are provided. An example apparatus includes an envelope regulator circuit to process, based on a parameterized model, an input signal to generate an envelope regulated signal; a digital predistortion (DPD) actuator circuit to process the envelope regulated signal and the input signal based on DPD coefficients associated with a nonlinearity characteristic of a nonlinear component; and a DPD adaptation circuit to update the DPD coefficients based on a feedback signal indicative of an output of the nonlinear component.
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公开(公告)号：US11665027B2
公开(公告)日：2023-05-30
申请号：US17375043
申请日：2021-07-14
Applicant: Analog Devices, Inc.
Inventor： Manish J. Manglani , Christopher Mayer
CPC classification number: H04L25/0264 , H04B1/401
Abstract: Devices exchange control signals with each other to ensure proper operation of an overall system. For instance, in a communication system, a baseband processor and a transceiver communicate with each other to exchange information for controlling the respective signal processing parts of the baseband processor and the transceiver. While Serial Peripheral Interfaces (SPIs) can be used, SPI can be extremely slow, and does not provide a protocol for allowing a complex set of control signals to be exchanged between the baseband processor and transceiver. The present disclosure describes a fast control interface which can support various modes of operation in allowing two devices to communicate with each other quickly and effectively.
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公开(公告)号：US10733141B2
公开(公告)日：2020-08-04
申请号：US16103711
申请日：2018-08-14
Applicant: Analog Devices, Inc.
Inventor： Manish J. Manglani , Shipra Bhal , Christopher Mayer
Abstract: This disclosure relates to a distributed processing system for configuring multiple processing channels. The distributed processing system includes a main processor, such as an ARM processor, communicatively coupled to a plurality of co-processors, such as stream processors. The co-processors can execute instructions in parallel with each other and interrupt the ARM processor. Longer latency instructions can be executed by the main processor and lower latency instructions can be executed by the co-processors. There are several ways that a stream can be triggered in the distributed processing system. In an embodiment, the distributed processing system is a stream processor system that includes an ARM processor and stream processors configured to access different register sets. The stream processors can include a main stream processor and stream processors in respective transmit and receive channels. The stream processor system can be implemented in a radio system to configure the radio for operation.
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公开(公告)号：US10659065B2
公开(公告)日：2020-05-19
申请号：US15957766
申请日：2018-04-19
Applicant: Analog Devices, Inc.
Inventor： Christopher Mayer , David J. McLaurin , Christopher W. Angell , Sudhir Desai , Steven R. Bal
Abstract: Apparatus and methods for phase synchronization of phase-locked loops (PLLs) are provided. In certain configurations, an RF communication system includes a PLL that generates one or more output clock signals and a phase synchronization circuit that synchronizes a phase of the PLL. The phase synchronization circuit includes a sampling circuit that generates samples by sampling the one or more output clock signals based on timing of a reference clock signal. Additionally, the phase synchronization circuit includes a phase difference calculation circuit that generates a phase difference signal based on the samples and a tracking digital phase signal representing the phase of the PLL. The phase synchronization circuit further includes a phase adjustment control circuit that provides a phase adjustment to the PLL based on the phase difference signal so as to synchronize the PLL.
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