-
公开(公告)号：US20170324419A1
公开(公告)日：2017-11-09
申请号：US15147408
申请日：2016-05-05
Applicant: ANALOG DEVICES, INC.
Inventor： Christopher Mayer , David J. McLaurin , Christopher W. Angell , Sudhir Desai , Steven R. Bal
CPC classification number: H03L7/1976 , H03L7/087 , H03L7/0891 , H03L7/091 , H03L7/093 , H03L7/23 , H03L7/235 , H04B7/0413 , H04L7/0331
Abstract: Apparatus and methods for phase synchronization of phase-locked loops (PLLs) are provided. In certain configurations, an RF communication system includes a PLL that generates one or more output clock signals and a phase synchronization circuit that synchronizes a phase of the PLL. The phase synchronization circuit includes a sampling circuit that generates samples by sampling the one or more output clock signals based on timing of a reference clock signal. Additionally, the phase synchronization circuit includes a phase difference calculation circuit that generates a phase difference signal based on the samples and a tracking digital phase signal representing the phase of the PLL. The phase synchronization circuit further includes a phase adjustment control circuit that provides a phase adjustment to the PLL based on the phase difference signal so as to synchronize the PLL.
-
公开(公告)号：US10659065B2
公开(公告)日：2020-05-19
申请号：US15957766
申请日：2018-04-19
Applicant: Analog Devices, Inc.
Inventor： Christopher Mayer , David J. McLaurin , Christopher W. Angell , Sudhir Desai , Steven R. Bal
Abstract: Apparatus and methods for phase synchronization of phase-locked loops (PLLs) are provided. In certain configurations, an RF communication system includes a PLL that generates one or more output clock signals and a phase synchronization circuit that synchronizes a phase of the PLL. The phase synchronization circuit includes a sampling circuit that generates samples by sampling the one or more output clock signals based on timing of a reference clock signal. Additionally, the phase synchronization circuit includes a phase difference calculation circuit that generates a phase difference signal based on the samples and a tracking digital phase signal representing the phase of the PLL. The phase synchronization circuit further includes a phase adjustment control circuit that provides a phase adjustment to the PLL based on the phase difference signal so as to synchronize the PLL.
-
公开(公告)号：US09787415B2
公开(公告)日：2017-10-10
申请号：US13826365
申请日：2013-03-14
Applicant: Analog Devices, Inc.
Inventor： Jianxun Fan , Reza Alavi , Steven R. Bal , David J. McLaurin
Abstract: A method and apparatus for estimating and compensating TX LO leakage using circuitry on a loopback path connecting the transmitter and receiver are provided. The TX LO leakage may be estimated by measuring the DC signal on the receiver, measuring the phase difference between the received LO signal and the receiver LO signal, and filtering LO harmonics that may arise from the use of non-linear mixers. The DC signal on the receiver may be measured by opening and closing the loopback path, or changing the gain of the loopback path, or flipping the phase of looped back TX signal. The method may be used in an initialization or tracking calibration scheme.
-
公开(公告)号：US11012201B2
公开(公告)日：2021-05-18
申请号：US14340461
申请日：2014-07-24
Applicant: Analog Devices, Inc.
Inventor： Raju Hormis , Steven R. Bal , Antonio Montalvo , David J. McLaurin , Martin McCormick
Abstract: A transmission module is provided that includes a transmitter, a loopback receiver, and a QEC controller. The QEC controller identifies quadrature imbalance in the transmitter based at least one a comparison of the data signals at the output of the loopback receiver with data signals at the input of the transmitter. Based on the comparison, the QEC controller can adjust one or more characteristics of the transmitter to correct quadrature errors in the transmitter.
-
Patent Agency Ranking
公开(公告)号：US09979408B2
公开(公告)日：2018-05-22
申请号：US15147408
申请日：2016-05-05
Applicant: ANALOG DEVICES, INC.
Inventor： Christopher Mayer , David J. McLaurin , Christopher W. Angell , Sudhir Desai , Steven R. Bal
CPC classification number: H03L7/1976 , H03L7/087 , H03L7/0891 , H03L7/091 , H03L7/093 , H03L7/23 , H03L7/235 , H04B7/0413 , H04L7/0331
Abstract: Apparatus and methods for phase synchronization of phase-locked loops (PLLs) are provided. In certain configurations, an RF communication system includes a PLL that generates one or more output clock signals and a phase synchronization circuit that synchronizes a phase of the PLL. The phase synchronization circuit includes a sampling circuit that generates samples by sampling the one or more output clock signals based on timing of a reference clock signal. Additionally, the phase synchronization circuit includes a phase difference calculation circuit that generates a phase difference signal based on the samples and a tracking digital phase signal representing the phase of the PLL. The phase synchronization circuit further includes a phase adjustment control circuit that provides a phase adjustment to the PLL based on the phase difference signal so as to synchronize the PLL.
-
公开(公告)号：US20150030103A1
公开(公告)日：2015-01-29
申请号：US14340461
申请日：2014-07-24
Applicant: Analog Devices, Inc.
Inventor： Raju Hormis , Steven R. Bal , Antonio Montalvo , David J. McLaurin , Martin McCormick
Abstract: A transmission module is provided that includes a transmitter, a loopback receiver, and a QEC controller. The QEC controller identifies quadrature imbalance in the transmitter based at least one a comparison of the data signals at the output of the loopback receiver with data signals at the input of the transmitter. Based on the comparison, the QEC controller can adjust one or more characteristics of the transmitter to correct quadrature errors in the transmitter.
Abstract translation: 提供了一种传输模块，其包括发射机，环回接收机和QEC控制器。 QEC控制器通过至少一个环回接收机输出端的数据信号与发射机输入端的数据信号进行比较，来识别发射机的正交不平衡。 基于比较，QEC控制器可以调整发射机的一个或多个特性来校正发射机的正交误差。
-
公开(公告)号：US20180294817A1
公开(公告)日：2018-10-11
申请号：US15957766
申请日：2018-04-19
Applicant: Analog Devices, Inc.
Inventor： Christopher Mayer , David J. McLaurin , Christopher W. Angell , Sudhir Desai , Steven R. Bal
Abstract: Apparatus and methods for phase synchronization of phase-locked loops (PLLs) are provided. In certain configurations, an RF communication system includes a PLL that generates one or more output clock signals and a phase synchronization circuit that synchronizes a phase of the PLL. The phase synchronization circuit includes a sampling circuit that generates samples by sampling the one or more output clock signals based on timing of a reference clock signal. Additionally, the phase synchronization circuit includes a phase difference calculation circuit that generates a phase difference signal based on the samples and a tracking digital phase signal representing the phase of the PLL. The phase synchronization circuit further includes a phase adjustment control circuit that provides a phase adjustment to the PLL based on the phase difference signal so as to synchronize the PLL.
-
公开(公告)号：US09300444B2
公开(公告)日：2016-03-29
申请号：US13951341
申请日：2013-07-25
Applicant: ANALOG DEVICES, INC
Inventor： Raju Hormis , Steven R. Bal , Kevin Glenn Gard , Jianxun Fan , David J. McLaurin , Antonio Montalvo
CPC classification number: H04L1/243 , H03F3/245 , H03F3/45475 , H03F2200/336 , H03F2203/45512 , H04B17/14 , H04B17/17 , H04B17/18 , H04B17/21 , H04L27/364 , H04L27/366
Abstract: A transmission module is provided that includes a transmitter, a loopback receiver, and a QEC controller. In a first state, the QEC controller calibrates the loopback receiver to remove quadrature imbalance in the loopback receiver. In a second state, a communication pathway is provided between the transmitter and the loopback receiver, and the QEC controller identifies quadrature imbalance in the transmitter based at least one a comparison of the data signals at the output of the loopback receiver with data signals at the input of the transmitter. Based on the comparison, the QEC controller can adjust one or more characteristics of the transmitter to correct quadrature errors in the transmitter.
Abstract translation: 提供了一种传输模块，其包括发射机，环回接收机和QEC控制器。 在第一种状态下，QEC控制器校准环回接收机以消除环回接收机中的正交不平衡。 在第二状态下，在发射机和环回接收机之间提供通信路径，并且QEC控制器基于环回接收机的输出端的数据信号与数据信号的比较， 发射机的输入。 基于比较，QEC控制器可以调整发射机的一个或多个特性来校正发射机的正交误差。
-
公开(公告)号：US20150030102A1
公开(公告)日：2015-01-29
申请号：US13951341
申请日：2013-07-25
Applicant: Analog Devices, Inc.
Inventor： Raju Hormis , Steven R. Bal , Kevin Glenn Gard , Jianxun Fan , David J. McLaurin , Antonio Montalvo
CPC classification number: H04L1/243 , H03F3/245 , H03F3/45475 , H03F2200/336 , H03F2203/45512 , H04B17/14 , H04B17/17 , H04B17/18 , H04B17/21 , H04L27/364 , H04L27/366
Abstract: A transmission module is provided that includes a transmitter, a loopback receiver, and a QEC controller. In a first state, the QEC controller calibrates the loopback receiver to remove quadrature imbalance in the loopback receiver. In a second state, a communication pathway is provided between the transmitter and the loopback receiver, and the QEC controller identifies quadrature imbalance in the transmitter based at least one a comparison of the data signals at the output of the loopback receiver with data signals at the input of the transmitter. Based on the comparison, the QEC controller can adjust one or more characteristics of the transmitter to correct quadrature errors in the transmitter.
Abstract translation: 提供了一种传输模块，其包括发射机，环回接收机和QEC控制器。 在第一种状态下，QEC控制器校准环回接收机以消除环回接收机中的正交不平衡。 在第二状态下，在发射机和环回接收机之间提供通信路径，并且QEC控制器基于环回接收机的输出端的数据信号与数据信号的比较， 发射机的输入。 基于比较，QEC控制器可以调整发射机的一个或多个特性来校正发射机的正交误差。
-
-
-
-
-
-
-
-
Search Results
9
records
(took 0.016 seconds)
