公开(公告)号：US10659065B2

公开(公告)日：2020-05-19

申请号：US15957766

申请日：2018-04-19

Applicant: Analog Devices, Inc.

Inventor： Christopher Mayer ,  David J. McLaurin ,  Christopher W. Angell ,  Sudhir Desai ,  Steven R. Bal

IPC: H03L7/197 ,  H03L7/087 ,  H03L7/23 ,  H03L7/089 ,  H03L7/091 ,  H03L7/093 ,  H04B7/0413 ,  H04L7/033

Abstract: Apparatus and methods for phase synchronization of phase-locked loops (PLLs) are provided. In certain configurations, an RF communication system includes a PLL that generates one or more output clock signals and a phase synchronization circuit that synchronizes a phase of the PLL. The phase synchronization circuit includes a sampling circuit that generates samples by sampling the one or more output clock signals based on timing of a reference clock signal. Additionally, the phase synchronization circuit includes a phase difference calculation circuit that generates a phase difference signal based on the samples and a tracking digital phase signal representing the phase of the PLL. The phase synchronization circuit further includes a phase adjustment control circuit that provides a phase adjustment to the PLL based on the phase difference signal so as to synchronize the PLL.

公开(公告)号：US20170324419A1

公开(公告)日：2017-11-09

申请号：US15147408

申请日：2016-05-05

Applicant: ANALOG DEVICES, INC.

Inventor： Christopher Mayer ,  David J. McLaurin ,  Christopher W. Angell ,  Sudhir Desai ,  Steven R. Bal

IPC: H03L7/197 ,  H03L7/093 ,  H03L7/089 ,  H03L7/091 ,  H04L7/033 ,  H04B7/0413

CPC classification number: H03L7/1976 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/091 ,  H03L7/093 ,  H03L7/23 ,  H03L7/235 ,  H04B7/0413 ,  H04L7/0331

Abstract: Apparatus and methods for phase synchronization of phase-locked loops (PLLs) are provided. In certain configurations, an RF communication system includes a PLL that generates one or more output clock signals and a phase synchronization circuit that synchronizes a phase of the PLL. The phase synchronization circuit includes a sampling circuit that generates samples by sampling the one or more output clock signals based on timing of a reference clock signal. Additionally, the phase synchronization circuit includes a phase difference calculation circuit that generates a phase difference signal based on the samples and a tracking digital phase signal representing the phase of the PLL. The phase synchronization circuit further includes a phase adjustment control circuit that provides a phase adjustment to the PLL based on the phase difference signal so as to synchronize the PLL.

公开(公告)号：US20180294817A1

公开(公告)日：2018-10-11

申请号：US15957766

申请日：2018-04-19

Applicant: Analog Devices, Inc.

Inventor： Christopher Mayer ,  David J. McLaurin ,  Christopher W. Angell ,  Sudhir Desai ,  Steven R. Bal

IPC: H03L7/197 ,  H03L7/23 ,  H03L7/087 ,  H04L7/033 ,  H03L7/089 ,  H03L7/093 ,  H03L7/091 ,  H04B7/0413

Abstract: Apparatus and methods for phase synchronization of phase-locked loops (PLLs) are provided. In certain configurations, an RF communication system includes a PLL that generates one or more output clock signals and a phase synchronization circuit that synchronizes a phase of the PLL. The phase synchronization circuit includes a sampling circuit that generates samples by sampling the one or more output clock signals based on timing of a reference clock signal. Additionally, the phase synchronization circuit includes a phase difference calculation circuit that generates a phase difference signal based on the samples and a tracking digital phase signal representing the phase of the PLL. The phase synchronization circuit further includes a phase adjustment control circuit that provides a phase adjustment to the PLL based on the phase difference signal so as to synchronize the PLL.

公开(公告)号：US09979408B2

公开(公告)日：2018-05-22

申请号：US15147408

申请日：2016-05-05

Applicant: ANALOG DEVICES, INC.

Inventor： Christopher Mayer ,  David J. McLaurin ,  Christopher W. Angell ,  Sudhir Desai ,  Steven R. Bal

IPC: H03L7/091 ,  H03L7/093 ,  H04B7/0413 ,  H03L7/087 ,  H03L7/23 ,  H03L7/197 ,  H03L7/089 ,  H04L7/033

CPC classification number: H03L7/1976 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/091 ,  H03L7/093 ,  H03L7/23 ,  H03L7/235 ,  H04B7/0413 ,  H04L7/0331

Abstract: Apparatus and methods for phase synchronization of phase-locked loops (PLLs) are provided. In certain configurations, an RF communication system includes a PLL that generates one or more output clock signals and a phase synchronization circuit that synchronizes a phase of the PLL. The phase synchronization circuit includes a sampling circuit that generates samples by sampling the one or more output clock signals based on timing of a reference clock signal. Additionally, the phase synchronization circuit includes a phase difference calculation circuit that generates a phase difference signal based on the samples and a tracking digital phase signal representing the phase of the PLL. The phase synchronization circuit further includes a phase adjustment control circuit that provides a phase adjustment to the PLL based on the phase difference signal so as to synchronize the PLL.