公开(公告)号：US10771074B1

公开(公告)日：2020-09-08

申请号：US16283194

申请日：2019-02-22

Applicant: Analog Devices, Inc.

Inventor： Paritosh Bhoraskar ,  Ahmed Mohamed Abdelatty Ali ,  Christopher Daniel Dillon

IPC: H03M1/12 ,  H03M1/00 ,  H03M1/08 ,  H03M1/80 ,  H03M1/10

Abstract: Comparators are implemented in many circuits, including analog-to-digital converters (ADCs). Some ADCs demand high bandwidth, low power consumption, and high speed. To address these requirements, a comparator circuit can be implemented without a separate pre-amplifier, where a sampling network drives a latch directly. Specifically, the comparator circuit integrates a pre-amplifier within the latch in a manner that ensures low power and high speed operation.

公开(公告)号：US09602121B2

公开(公告)日：2017-03-21

申请号：US14793524

申请日：2015-07-07

Applicant: ANALOG DEVICES, INC.

Inventor： Ahmed Mohamed Abdelatty Ali ,  Paritosh Bhoraskar ,  Huseyin Dinc ,  Andrew Stacy Morgan

IPC: H03M1/10 ,  H03M1/36

CPC classification number: H03M1/1028 ,  H03M1/1023 ,  H03M1/168 ,  H03M1/361

Abstract: A pipeline analog-to-digital converter (ADC) converts an analog input signal over several stages, where a stage generates a residue for the subsequent stage to digitize. The residue is generated by coarsely quantizing the analog input signal to generate a digital code, which is used to reconstruct the analog input signal, and the residue is the difference between the analog input signal and the reconstructed version of the analog input signal. The coarse quantization can have errors which are attributed to comparator offsets and bandwidth mismatch. To estimate the comparator offsets while being insensitive to bandwidth mismatch, peak and trough detectors are used to track maximum and minimum values of the residue or the output of the ADC over time, and an expected value estimating the comparator offset can be computed based on the maximum and minimum values. The expected value advantageously “averages” out the bandwidth mismatch contribution to the offset.