公开(公告)号：US11121713B1

公开(公告)日：2021-09-14

申请号：US17007126

申请日：2020-08-31

Applicant: Analog Devices, Inc.

Inventor： Scott G. Bardsley ,  Huseyin Dinc

IPC: H03K3/012 ,  H03K3/356 ,  H03K19/00 ,  H03K19/0185 ,  H03K17/687 ,  H03K17/10

Abstract: An example boosted switch driver circuit includes two branches. The first branch includes a first transistor. The second branch includes a second transistor and a level shifter circuit. One of the transistors is an N-type transistor and the other one is a P-type transistor. The circuit is configured to split an input clock signal between the first branch and the second branch, so that a portion of the input clock signal split to the first branch is provided to the first transistor, and a portion of the input clock signal split to the second branch is level-shifted by the level shifter circuit to generate a level-shifted input clock signal and the level-shifted input clock signal is provided to the second transistor. The circuit is further configured to combine an output of the first transistor and an output of the second transistor to generate an output clock signal.

公开(公告)号：US09602121B2

公开(公告)日：2017-03-21

申请号：US14793524

申请日：2015-07-07

Applicant: ANALOG DEVICES, INC.

Inventor： Ahmed Mohamed Abdelatty Ali ,  Paritosh Bhoraskar ,  Huseyin Dinc ,  Andrew Stacy Morgan

IPC: H03M1/10 ,  H03M1/36

CPC classification number: H03M1/1028 ,  H03M1/1023 ,  H03M1/168 ,  H03M1/361

Abstract: A pipeline analog-to-digital converter (ADC) converts an analog input signal over several stages, where a stage generates a residue for the subsequent stage to digitize. The residue is generated by coarsely quantizing the analog input signal to generate a digital code, which is used to reconstruct the analog input signal, and the residue is the difference between the analog input signal and the reconstructed version of the analog input signal. The coarse quantization can have errors which are attributed to comparator offsets and bandwidth mismatch. To estimate the comparator offsets while being insensitive to bandwidth mismatch, peak and trough detectors are used to track maximum and minimum values of the residue or the output of the ADC over time, and an expected value estimating the comparator offset can be computed based on the maximum and minimum values. The expected value advantageously “averages” out the bandwidth mismatch contribution to the offset.

公开(公告)号：US09397682B2

公开(公告)日：2016-07-19

申请号：US14262274

申请日：2014-04-25

Applicant: ANALOG DEVICES, INC.

Inventor： Huseyin Dinc ,  Ahmed Mohamed Abdelatty Ali

IPC: H03K19/0175 ,  H03K19/094 ,  H03M1/12 ,  H03M1/16 ,  H03F3/50 ,  H03K19/0185 ,  H03M1/14 ,  H03M1/38

CPC classification number: H03M1/12 ,  H03F3/505 ,  H03K19/018585 ,  H03M1/145 ,  H03M1/164 ,  H03M1/167 ,  H03M1/38

Abstract: Circuits for generating voltage references are common in electronics. For example, these circuits are used in analog-to-digital converters, which convert an analog signal into its digital representation by comparing analog input signals against one or more voltage references provided by those circuits. In many applications, the speed and accuracy of such voltage references are very important. The speed of the voltage references is related to the physical properties of the devices in the circuit. The accuracy of the voltage reference is directly related to the circuit's ability to trim the full-scale voltage output. The present disclosure describes a fast and efficient reference buffer with a wide trim range which is particular suitable for submicron processes and high speed applications. The reference buffer comprises a plurality of diode-connected transistors, which can be selected to turn on or off using a controller to provide a wide trim range.

Abstract translation: 用于产生电压基准的电路在电子设备中很常见。 例如，这些电路用于模数转换器，其通过将模拟输入信号与由这些电路提供的一个或多个电压参考值相比较来将模拟信号转换成其数字表示。 在许多应用中，这种参考电压的速度和精度非常重要。 电压基准的速度与电路中器件的物理性质有关。 电压参考的精度直接关系到电路修整满量程电压输出的能力。 本公开描述了一种具有宽的修剪范围的快速和有效的参考缓冲器，其特别适用于亚微米工艺和高速应用。 参考缓冲器包括多个二极管连接的晶体管，其可以选择使用控制器导通或关断以提供宽的修整范围。

公开(公告)号：US10763878B2

公开(公告)日：2020-09-01

申请号：US16364134

申请日：2019-03-25

Applicant: Analog Devices, Inc.

Inventor： Ahmed Mohamed Abdelatty Ali ,  Paridhi Gulati ,  Bryan S. Puckett ,  Huseyin Dinc

IPC: H03M1/10 ,  H03M1/06

Abstract: Background calibration techniques can effectively to correct for memory, kick-back, and order-dependent errors in interleaved switched-capacitor track-and-hold (T/H) circuits and amplifiers. The techniques calibrate for errors in both the track/sample phase and the hold-phase, and account for the effects of interleaving, buffer/amplifier sharing, incomplete resetting, incomplete settling, chopping, and randomization on the offset, gain, memory, and kick-back errors. Moreover, the techniques can account for order-dependent and state-dependent hold-phase non-linearities. By correcting for these errors, the proposed techniques improve the noise performance, linearity, gain/offset matching, frequency response (and bandwidth), and order-dependence errors. The techniques also help increase the speed (sample rate and bandwidth) and linearity of T/H circuits and amplifiers while simplifying the analog circuitry and clocking needed. These techniques comprehensively account for various memory, kick-back, and order-dependent effects in a unified framework.

公开(公告)号：US20250167793A1

公开(公告)日：2025-05-22

申请号：US18933599

申请日：2024-10-31

Applicant: Analog Devices, Inc.

Inventor： Nicholas S. Zakas ,  Huseyin Dinc ,  Jesse Bankman

IPC: H03M1/10

Abstract: An analog-to-digital converter (ADC) system for switching between a first operating mode and a second operating mode, where both the first operating mode and the second operating mode can include post-calibration analog-to-digital conversions, where a hardware circuitry configuration of the second operating mode can differ from a hardware circuitry configuration of the first operating mode, can include hardware circuitry. The ADC system can also include a controller, which can be configured to control the hardware circuitry to control switching between the first operating mode and the second operating mode in response to a command to switch from the first operating mode to the second operating mode. This can include to transmit second mode configuration information and second mode calibration information to the hardware circuitry, where the second mode configuration information can include values to configure the hardware circuitry to operate in the second operating mode and the second mode calibration information can include values to calibrate the ADC system while operating in the second operating mode.