公开(公告)号：US20200343721A1

公开(公告)日：2020-10-29

申请号：US16946917

申请日：2020-07-10

Applicant: Analog Devices, Inc.

Inventor： Srivatsan Parthasarathy ,  Javier Alejandro Salcedo ,  James Zhao

IPC: H02H9/04 ,  H02H9/00 ,  H01L27/02

Abstract: High voltage clamps with transient activation and activation release control are provided herein. In certain configurations, an integrated circuit (IC) includes a clamp electrically connected between a first node and a second node and having a control input. The IC further includes a first resistor-capacitor (RC) circuit that activates a detection signal in response to detecting a transient overstress event between the first node and the second node, an active feedback circuit that provides feedback from the first node to the control input of the clamp in response to activation of the detection signal, a second RC circuit that activates a shutdown signal after detecting passage of the transient overstress event based on low pass filtering a voltage difference between the first node and the second node, and a clamp shutdown circuit that turns off the clamp via the control input in response to activation of the shutdown signal.

公开(公告)号：US10734806B2

公开(公告)日：2020-08-04

申请号：US15215938

申请日：2016-07-21

Applicant: ANALOG DEVICES, INC.

Inventor： James Zhao ,  Javier Alejandro Salcedo ,  Srivatsan Parthasarathy

IPC: H02H9/04 ,  H02H9/00 ,  H01L27/02

Abstract: High voltage clamps with active activation and activation-release control are provided herein. In certain configurations, a clamp can have scalable operating clamping voltage level and can be used to protect the electrical circuit connected to a power supply of a semiconductor chip from damage from an overstress event, such as electrostatic discharge (ESD) events. The pins of the power supply are actively monitored to detect when an overstress event is present, and the clamp is turned-on in response to detecting the overstress event. A timer is used to shut down the clamp after a time delay from detecting the overstress event, thereby providing a false detection shutdown mechanism that prevents the protection clamp from getting falsely activated and remain in the on-state during normal circuit operation.

公开(公告)号：US10700056B2

公开(公告)日：2020-06-30

申请号：US16125319

申请日：2018-09-07

Applicant: ANALOG DEVICES, INC.

Inventor： James Zhao ,  Javier Alejandro Salcedo ,  Srivatsan Parthasarathy

IPC: H01L27/02 ,  H01L29/417 ,  H01L27/06 ,  H01L29/08 ,  H01L29/06 ,  H01L29/74 ,  H02H9/04 ,  B60R16/023

Abstract: A communication interface protection device includes a first electrical overstress (EOS) protection switch electrically connected to a first terminal and a second EOS protection switch electrically connected to a second terminal. Each of the first and second EOS protection switches includes a first semiconductor-controlled rectifier (SCR) and a second SCR and a first diode having a cathode electrically connected to an anode of the first SCR and a second diode having a cathode electrically connected to an anode of the second SCR. The first EOS protection device is configured to be activated in response to an EOS condition that causes a first bias between the first and second terminals, and wherein the second EOS protection device is configured to be activated in response to an EOS condition that causes a second bias between the first and second terminals.

公开(公告)号：US20200083212A1

公开(公告)日：2020-03-12

申请号：US16125319

申请日：2018-09-07

Applicant: ANALOG DEVICES, INC.

Inventor： James Zhao ,  Javier Alejandro Salcedo ,  Srivatsan Parthasarathy

IPC: H01L27/02 ,  H02H9/04 ,  H01L29/74 ,  H01L29/08 ,  H01L29/417 ,  H01L29/06 ,  H01L27/06 ,  B60R16/023

Abstract: A communication interface protection device includes a first electrical overstress (EOS) protection switch electrically connected to a first terminal and a second EOS protection switch electrically connected to a second terminal. Each of the first and second EOS protection switches includes a first semiconductor-controlled rectifier (SCR) and a second SCR and a first diode having a cathode electrically connected to an anode of the first SCR and a second diode having a cathode electrically connected to an anode of the second SCR. The first EOS protection device is configured to be activated in response to an EOS condition that causes a first bias between the first and second terminals, and wherein the second EOS protection device is configured to be activated in response to an EOS condition that causes a second bias between the first and second terminals.

公开(公告)号：US10404059B2

公开(公告)日：2019-09-03

申请号：US15428535

申请日：2017-02-09

Applicant: ANALOG DEVICES, INC.

Inventor： Javier Alejandro Salcedo ,  Srivatsan Parthasarathy ,  Linfeng He ,  Yuanzhong Zhou

IPC: H02H7/20 ,  H01L23/528 ,  H01L27/02 ,  H01L27/092

Abstract: Distributed switches to suppress transient electrical overstress-induced latch-up are provided. In certain configurations, an integrated circuit (IC) or semiconductor chip includes a transient electrical overstress detection circuit that activates a transient overstress detection signal in response to detecting a transient electrical overstress event between a pair of power rails. The IC further includes mixed-signal circuits and latch-up suppression switches distributed across the IC, and the latch-up suppression switches temporarily clamp the power rails to one another in response to activation of the transient overstress detection signal to inhibit latch-up of the mixed-signal circuits.

公开(公告)号：US10177566B2

公开(公告)日：2019-01-08

申请号：US15188626

申请日：2016-06-21

Applicant: ANALOG DEVICES, INC.

Inventor： James Zhao ,  Javier Alejandro Salcedo ,  Srivatsan Parthasarathy

IPC: H02H9/04 ,  H01L27/02

Abstract: Apparatus and methods for actively-controlled trigger and latch release thyristor are provided. In certain configurations, an actively-controlled protection circuit includes an overvoltage sense circuit, a thyristor or silicon controlled rectifier (SCR) that is electrically connected between a signal node and a discharge node, and an active trigger and latch release circuit. The overvoltage sense circuit controls a voltage of a dummy supply node based on a voltage of the signal node, and the active trigger and latch release circuit detects presence of a transient overstress event at the signal node based on the voltage of the dummy supply node. The active trigger and latch release circuit provides one or more trigger signals to the SCR to control the SCR's activation voltage, and the active trigger and latch release circuit activates or deactivates the one or more trigger signals based on whether or not the transient overstress event is detected.

公开(公告)号：US10158029B2

公开(公告)日：2018-12-18

申请号：US15050876

申请日：2016-02-23

Applicant: ANALOG DEVICES, INC.

Inventor： Srivatsan Parthasarathy ,  Javier Alejandro Salcedo

IPC: H01L29/872 ,  H01L29/778 ,  H01L27/02 ,  H01L29/205 ,  H01L27/06 ,  H01L29/812 ,  H01L29/10

Abstract: Apparatus and methods for compound semiconductor protection clamps are provided herein. In certain configurations, a compound semiconductor protection clamp includes a resistor-capacitor (RC) trigger network and a metal-semiconductor field effect transistor (MESFET) clamp. The RC trigger network detects when an ESD/EOS event is present between a first node and a second node, and activates the MESFET clamp in response to detecting the ESD/EOS event. When the MESFET clamp is activated, the MESFET clamp provides a low impedance path between the first and second nodes, thereby providing ESD/EOS protection. When deactivated, the MESFET clamp provides high impedance between the first and second nodes, and thus operates with low leakage current and small static power dissipation.

公开(公告)号：US20140167105A1

公开(公告)日：2014-06-19

申请号：US14068869

申请日：2013-10-31

Applicant: Analog Devices, Inc.

Inventor： Javier Alejandro Salcedo ,  Srivatsan Parthasarathy

IPC: H01L27/02 ,  H01L21/8249

CPC classification number: H01L27/0262 ,  H01L27/0255

Abstract: Apparatus and methods for monolithic data conversion interface protection are provided herein. In certain implementations, a protection device includes a first silicon controlled rectifier (SCR) and a first diode for providing protection between a signal node and a power high supply node, a second SCR and a second diode for providing protection between the signal node and a power low supply node, and a third SCR and a third diode for providing protection between the power high supply node and the power low supply node. The SCR and diode structures are integrated in a common circuit layout, such that certain wells and active regions are shared between structures. Configuring the protection device in this manner enables in-suit input/output interface protection using a single cell. The protection device is suitable for monolithic data conversion interface protection in sub 3V operation.

Abstract translation: 本文提供了单片数据转换接口保护的装置和方法。 在某些实施方案中，保护装置包括第一可控硅整流器（SCR）和第一二极管，用于在信号节点和功率高电源节点之间提供保护，第二SCR和第二二极管用于在信号节点和 电源低电源节点，以及用于在电源高供电节点和电源低电源节点之间提供保护的第三SCR和第三二极管。 SCR和二极管结构集成在公共电路布局中，使得某些阱和有源区域在结构之间共享。 以这种方式配置保护设备可以使用单个单元进行适合的输入/输出接口保护。 该保护装置适用于3V以下的单片数据转换接口保护。

公开(公告)号：US08730630B2

公开(公告)日：2014-05-20

申请号：US13863155

申请日：2013-04-15

Applicant: Analog Devices, Inc.

Inventor： Srivatsan Parthasarathy ,  Javier A. Salcedo

IPC: H02H9/00

CPC classification number: H02H3/22 ,  H01L27/0259 ,  H02H9/046

Abstract: Apparatuses and methods for providing transient electrical event protection are disclosed. In one embodiment, an apparatus comprises a detection and timing circuit, a current amplification circuit, and a clamping circuit. The detection and timing circuit is configured to detect a presence or absence of a transient electrical event at a first node, and to generate a first current for a first duration upon detection of the transient electrical event. The current amplification circuit is configured to receive the first current from the detection and timing circuit and to amplify the first current to generate a second current. The clamping circuit is electrically connected between the first node and a second node and receives the second current for activation. The clamping circuit is configured to activate a low impedance path between the first and second nodes in response to the second current, and to otherwise deactivate the low impedance path.

Abstract translation: 公开了用于提供瞬时电气事件保护的装置和方法。 在一个实施例中，一种装置包括检测和定时电路，电流放大电路和钳位电路。 检测和定时电路被配置为检测在第一节点处的瞬时电事件的存在或不存在，并且在检测到瞬态电事件时产生第一持续时间的第一电流。 电流放大电路被配置为从检测和定时电路接收第一电流并且放大第一电流以产生第二电流。 钳位电路电连接在第一节点和第二节点之间，并接收用于激活的第二电流。 钳位电路被配置为响应于第二电流来激活第一和第二节点之间的低阻抗路径，并且否则去激活低阻抗路径。

公开(公告)号：US20140133055A1

公开(公告)日：2014-05-15

申请号：US13673896

申请日：2012-11-09

Applicant: ANALOG DEVICES, INC.

Inventor： Srivatsan Parthasarathy ,  Javier Alejandro Salcedo

IPC: H02H9/04

CPC classification number: H02H9/041 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Apparatus and methods for active detection, timing, and protection related to transient electrical events are disclosed. A detection circuit can generate a first activation signal in response to a transient electrical stress event across a first node and a second node. A blocking circuit is configured to bias the base of a first driver bipolar transistor to slow down discharge of accumulated base charge of a first driver bipolar transistor, which permits the first driver bipolar transistor to remain activated for a longer period of time than had the base of the first driver bipolar transistor been biased to the same voltage as the emitter of the first bipolar transistor. Shut-off circuitry can be included in some embodiments to prevent a discharge circuit from activating during normal operating conditions.

Abstract translation: 公开了与瞬时电气事件相关的主动检测，定时和保护的装置和方法。 检测电路可以响应于穿过第一节点和第二节点的瞬时电应力事件而产生第一激活信号。 阻塞电路被配置为偏置第一驱动器双极晶体管的基极以减慢第一驱动器双极晶体管的累积基极电荷的放电，这允许第一驱动器双极晶体管保持激活更长的时间段，而不是基极 的第一驱动器双极晶体管被偏置到与第一双极晶体管的发射极相同的电压。 在一些实施例中可以包括关断电路以防止放电电路在正常操作条件下激活。