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公开(公告)号：US20170366002A1
公开(公告)日：2017-12-21
申请号：US15188626
申请日：2016-06-21
Applicant: ANALOG DEVICES, INC.
Inventor： James Zhao , Javier Alejandro Salcedo , Srivatsan Parthasarathy
CPC classification number: H02H9/046 , H01L27/0262 , H01L2224/48091 , H01L2224/48145 , H01L2224/48247 , H01L2924/181 , H02H9/044 , H01L2924/00014 , H01L2924/00012
Abstract: Apparatus and methods for actively-controlled trigger and latch release thyristor are provided. In certain configurations, an actively-controlled protection circuit includes an overvoltage sense circuit, a thyristor or silicon controlled rectifier (SCR) that is electrically connected between a signal node and a discharge node, and an active trigger and latch release circuit. The overvoltage sense circuit controls a voltage of a dummy supply node based on a voltage of the signal node, and the active trigger and latch release circuit detects presence of a transient overstress event at the signal node based on the voltage of the dummy supply node. The active trigger and latch release circuit provides one or more trigger signals to the SCR to control the SCR's activation voltage, and the active trigger and latch release circuit activates or deactivates the one or more trigger signals based on whether or not the transient overstress event is detected.
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公开(公告)号：US09478608B2
公开(公告)日：2016-10-25
申请号：US14546703
申请日：2014-11-18
Applicant: Analog Devices, Inc.
Inventor： Javier Alejandro Salcedo , James Zhao , Juan Luo
IPC: H01L27/02 , H01L23/62 , H01L29/06 , H01L21/761
CPC classification number: H01L29/0646 , H01L21/761 , H01L23/62 , H01L27/0248 , H01L27/0259 , H01L27/0262 , H01L27/0292 , H01L29/0653 , H01L29/73 , H01L29/7835 , H01L2924/0002 , H01L2924/00
Abstract: Apparatus and methods for transceiver interface overvoltage clamping are provided. In certain configurations, an interface device includes a first p-type well region and a second p-type well region in an n-type isolation structure. Additionally, the clamp device includes a first p-type active region and a first n-type active region in the first p-type well region and electrically connected to a first terminal of the clamp device. Furthermore, the clamp device includes a second p-type active region and a second n-type active region in the second p-type well region and electrically connected to a second terminal of the clamp device. The n-type isolation structure is in a p-type region of a semiconductor substrate, and electrically isolates the first and second p-type well regions from the p-type substrate region. The clamp device further includes a blocking voltage tuning structure positioned between the first and second n-type active regions.
Abstract translation: 提供收发器接口过电压钳位的装置和方法。 在某些配置中，接口装置包括n型隔离结构中的第一p型阱区和第二p型阱区。 此外，夹持装置包括第一p型阱区中的第一p型有源区和第一n型有源区，并且电连接到钳位装置的第一端。 此外，夹持装置在第二p型阱区域中包括第二p型有源区和第二n型有源区，并且电连接到钳位装置的第二端。 n型隔离结构在半导体衬底的p型区域中，并将第一和第二p型阱区与p型衬底区电隔离。 钳位装置还包括位于第一和第二n型有源区之间的阻挡电压调谐结构。
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公开(公告)号：US20160204096A1
公开(公告)日：2016-07-14
申请号：US14594394
申请日：2015-01-12
Applicant: Analog Devices, Inc.
Inventor： James Zhao , Javier Alejandro Salcedo
IPC: H01L27/02 , H03K17/567 , H01L29/06 , H01L21/8222 , H01L49/02 , H01L29/10
CPC classification number: H01L27/0262 , H01L21/8222 , H01L28/20 , H01L29/0638 , H01L29/0649 , H01L29/1095 , H01L29/861 , H03K17/567
Abstract: Low leakage bidirectional clamps and methods of forming the same are provided. In certain configurations, a bidirectional clamp includes a first p-well region, a second p-well region, and an n-well region positioned between the first and second p-wells regions. The bidirectional clamp further includes two or more oxide regions over the n-well region, and one or more n-type active (N+) dummy blocking current regions are positioned between the oxide regions. The one or more N+ dummy leakage current blocking regions interrupt an electrical path from the first p-type well region to the second p-type well region along interfaces between the n-well region and the oxide regions. Thus, even when charge accumulates at the interfaces due to extended high voltage, e.g., >60V, and/or high temperature operation (e.g., >125° C.), the N+ dummy leakage current blocking regions inhibit charge trapping-induced leakage current.
Abstract translation: 提供了低泄漏双向夹具及其形成方法。 在某些配置中，双向钳位包括第一p阱区，第二p阱区和位于第一和第二p阱区之间的n阱区。 双向夹具还包括在n阱区域上的两个或更多个氧化物区域，并且一个或多个n型有源（N +）虚拟阻挡电流区域位于氧化物区域之间。 一个或多个N +虚设泄漏电流阻断区域沿着n阱区域和氧化物区域之间的界面中断从第一p型阱区域到第二p型阱区域的电路径。 因此，即使当由于延长的高电压（例如> 60V）和/或高温操作（例如> 125℃）在接口处累积电荷时，N +虚设泄漏电流阻挡区域抑制电荷捕获诱发的漏电流 。
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公开(公告)号：US10068894B2
公开(公告)日：2018-09-04
申请号：US14594394
申请日：2015-01-12
Applicant: Analog Devices, Inc.
Inventor： James Zhao , Javier Alejandro Salcedo
IPC: H01L27/02 , H01L21/8222 , H01L49/02 , H01L29/06 , H01L29/10 , H03K17/567 , H01L29/861
Abstract: Low leakage bidirectional clamps and methods of forming the same are provided. In certain configurations, a bidirectional clamp includes a first p-well region, a second p-well region, and an n-well region positioned between the first and second p-wells regions. The bidirectional clamp further includes two or more oxide regions over the n-well region, and one or more n-type active (N+) dummy blocking current regions are positioned between the oxide regions. The one or more N+ dummy leakage current blocking regions interrupt an electrical path from the first p-type well region to the second p-type well region along interfaces between the n-well region and the oxide regions. Thus, even when charge accumulates at the interfaces due to extended high voltage, e.g., >60V, and/or high temperature operation (e.g., >125° C.), the N+ dummy leakage current blocking regions inhibit charge trapping-induced leakage current.
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公开(公告)号：US11569658B2
公开(公告)日：2023-01-31
申请号：US16946917
申请日：2020-07-10
Applicant: Analog Devices, Inc.
Inventor： Srivatsan Parthasarathy , Javier Alejandro Salcedo , James Zhao
Abstract: High voltage clamps with transient activation and activation release control are provided herein. In certain configurations, an integrated circuit (IC) includes a clamp electrically connected between a first node and a second node and having a control input. The IC further includes a first resistor-capacitor (RC) circuit that activates a detection signal in response to detecting a transient overstress event between the first node and the second node, an active feedback circuit that provides feedback from the first node to the control input of the clamp in response to activation of the detection signal, a second RC circuit that activates a shutdown signal after detecting passage of the transient overstress event based on low pass filtering a voltage difference between the first node and the second node, and a clamp shutdown circuit that turns off the clamp via the control input in response to activation of the shutdown signal.
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Patent Agency Ranking
公开(公告)号：US20180026440A1
公开(公告)日：2018-01-25
申请号：US15215938
申请日：2016-07-21
Applicant: ANALOG DEVICES, INC.
Inventor： James Zhao , Javier Alejandro Salcedo , Srivatsan Parthasarathy
IPC: H02H9/04
Abstract: High voltage clamps with active activation and activation-release control are provided herein. In certain configurations, a clamp can have scalable operating clamping voltage level and can be used to protect the electrical circuit connected to a power supply of a semiconductor chip from damage from an overstress event, such as electrostatic discharge (ESD) events. The pins of the power supply are actively monitored to detect when an overstress event is present, and the clamp is turned-on in response to detecting the overstress event. A timer is used to shut down the clamp after a time delay from detecting the overstress event, thereby providing a false detection shutdown mechanism that prevents the protection clamp from getting falsely activated and remain in the on-state during normal circuit operation.
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公开(公告)号：US20200343721A1
公开(公告)日：2020-10-29
申请号：US16946917
申请日：2020-07-10
Applicant: Analog Devices, Inc.
Inventor： Srivatsan Parthasarathy , Javier Alejandro Salcedo , James Zhao
Abstract: High voltage clamps with transient activation and activation release control are provided herein. In certain configurations, an integrated circuit (IC) includes a clamp electrically connected between a first node and a second node and having a control input. The IC further includes a first resistor-capacitor (RC) circuit that activates a detection signal in response to detecting a transient overstress event between the first node and the second node, an active feedback circuit that provides feedback from the first node to the control input of the clamp in response to activation of the detection signal, a second RC circuit that activates a shutdown signal after detecting passage of the transient overstress event based on low pass filtering a voltage difference between the first node and the second node, and a clamp shutdown circuit that turns off the clamp via the control input in response to activation of the shutdown signal.
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公开(公告)号：US10734806B2
公开(公告)日：2020-08-04
申请号：US15215938
申请日：2016-07-21
Applicant: ANALOG DEVICES, INC.
Inventor： James Zhao , Javier Alejandro Salcedo , Srivatsan Parthasarathy
Abstract: High voltage clamps with active activation and activation-release control are provided herein. In certain configurations, a clamp can have scalable operating clamping voltage level and can be used to protect the electrical circuit connected to a power supply of a semiconductor chip from damage from an overstress event, such as electrostatic discharge (ESD) events. The pins of the power supply are actively monitored to detect when an overstress event is present, and the clamp is turned-on in response to detecting the overstress event. A timer is used to shut down the clamp after a time delay from detecting the overstress event, thereby providing a false detection shutdown mechanism that prevents the protection clamp from getting falsely activated and remain in the on-state during normal circuit operation.
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公开(公告)号：US10700056B2
公开(公告)日：2020-06-30
申请号：US16125319
申请日：2018-09-07
Applicant: ANALOG DEVICES, INC.
Inventor： James Zhao , Javier Alejandro Salcedo , Srivatsan Parthasarathy
IPC: H01L27/02 , H01L29/417 , H01L27/06 , H01L29/08 , H01L29/06 , H01L29/74 , H02H9/04 , B60R16/023
Abstract: A communication interface protection device includes a first electrical overstress (EOS) protection switch electrically connected to a first terminal and a second EOS protection switch electrically connected to a second terminal. Each of the first and second EOS protection switches includes a first semiconductor-controlled rectifier (SCR) and a second SCR and a first diode having a cathode electrically connected to an anode of the first SCR and a second diode having a cathode electrically connected to an anode of the second SCR. The first EOS protection device is configured to be activated in response to an EOS condition that causes a first bias between the first and second terminals, and wherein the second EOS protection device is configured to be activated in response to an EOS condition that causes a second bias between the first and second terminals.
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公开(公告)号：US20200083212A1
公开(公告)日：2020-03-12
申请号：US16125319
申请日：2018-09-07
Applicant: ANALOG DEVICES, INC.
Inventor： James Zhao , Javier Alejandro Salcedo , Srivatsan Parthasarathy
IPC: H01L27/02 , H02H9/04 , H01L29/74 , H01L29/08 , H01L29/417 , H01L29/06 , H01L27/06 , B60R16/023
Abstract: A communication interface protection device includes a first electrical overstress (EOS) protection switch electrically connected to a first terminal and a second EOS protection switch electrically connected to a second terminal. Each of the first and second EOS protection switches includes a first semiconductor-controlled rectifier (SCR) and a second SCR and a first diode having a cathode electrically connected to an anode of the first SCR and a second diode having a cathode electrically connected to an anode of the second SCR. The first EOS protection device is configured to be activated in response to an EOS condition that causes a first bias between the first and second terminals, and wherein the second EOS protection device is configured to be activated in response to an EOS condition that causes a second bias between the first and second terminals.
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