公开(公告)号：US20180226788A1

公开(公告)日：2018-08-09

申请号：US15428535

申请日：2017-02-09

Applicant: ANALOG DEVICES, INC.

Inventor： Javier Alejandro Salcedo ,  Srivatsan Parthasarathy ,  Linfeng He ,  Yuanzhong Zhou

IPC: H02H7/20 ,  H01L23/528 ,  H01L27/02 ,  H01L27/092

CPC classification number: H02H7/205 ,  H01L23/5286 ,  H01L27/0248 ,  H01L27/0262 ,  H01L27/0921

Abstract: Distributed switches to suppress transient electrical overstress-induced latch-up are provided. In certain configurations, an integrated circuit (IC) or semiconductor chip includes a transient electrical overstress detection circuit that activates a transient overstress detection signal in response to detecting a transient electrical overstress event between a pair of power rails. The IC further includes mixed-signal circuits and latch-up suppression switches distributed across the IC, and the latch-up suppression switches temporarily clamp the power rails to one another in response to activation of the transient overstress detection signal to inhibit latch-up of the mixed-signal circuits.

公开(公告)号：US09831666B2

公开(公告)日：2017-11-28

申请号：US14797770

申请日：2015-07-13

Applicant: ANALOG DEVICES, INC.

Inventor： Srivatsan Parthasarathy ,  Javier Alejandro Salcedo ,  Rodrigo Carrillo-Ramirez

IPC: H02H9/04 ,  H01L27/02

CPC classification number: H02H9/046 ,  H01L27/0248 ,  H01L27/0266 ,  H02H9/04

Abstract: Apparatus and methods for electrostatic discharge (ESD) protection of radio frequency circuits are provided. In certain configurations, an integrated circuit includes a first pin, a second pin, a forward ESD protection circuit, and a reverse ESD protection circuit. The forward ESD protection circuit includes one or more P+/N-EPI diodes, one or more ESD protection devices, and one or more P-EPI/N+ diodes electrically connected in series between the first pin and the second pin. A first P+/N-EPI diode of the one or more P+/N-EPI diodes includes an anode electrically connected to the first pin. The reverse ESD protection circuit comprising one or more P+/N-EPI diodes, one or more ESD protection devices, and one or more P-EPI/N+ diodes electrically connected in series between the second pin and the first pin. A first P-EPI/N+ diode of the one or more P-EPI/N+ diodes includes a cathode electrically connected to the first pin.

公开(公告)号：US20160336740A1

公开(公告)日：2016-11-17

申请号：US14797770

申请日：2015-07-13

Applicant: ANALOG DEVICES, INC.

Inventor： Srivatsan Parthasarathy ,  Javier Alejandro Salcedo ,  Rodrigo Carrillo-Ramirez

IPC: H02H9/04

CPC classification number: H02H9/046 ,  H01L27/0248 ,  H01L27/0266 ,  H02H9/04

Abstract: Apparatus and methods for electrostatic discharge (ESD) protection of radio frequency circuits are provided. In certain configurations, an integrated circuit includes a first pin, a second pin, a forward ESD protection circuit, and a reverse ESD protection circuit. The forward ESD protection circuit includes one or more P+/N-EPI diodes, one or more ESD protection devices, and one or more P-EPI/N+ diodes electrically connected in series between the first pin and the second pin. A first P+/N-EPI diode of the one or more P+/N-EPI diodes includes an anode electrically connected to the first pin. The reverse ESD protection circuit comprising one or more P+/N-EPI diodes, one or more ESD protection devices, and one or more P-EPI/N+ diodes electrically connected in series between the second pin and the first pin. A first P-EPI/N+ diode of the one or more P-EPI/N+ diodes includes a cathode electrically connected to the first pin.

Abstract translation: 提供射频电路的静电放电（ESD）保护装置和方法。 在某些配置中，集成电路包括第一引脚，第二引脚，正向ESD保护电路和反向ESD保护电路。 正向ESD保护电路包括一个或多个P + / N-EPI二极管，一个或多个ESD保护器件以及串联在第一引脚和第二引脚之间电连接的一个或多个P-EPI / N +二极管。 一个或多个P + / N-EPI二极管的第一P + / N-EPI二极管包括电连接到第一引脚的阳极。 反向ESD保护电路包括一个或多个P + / N-EPI二极管，一个或多个ESD保护器件以及串联在第二引脚和第一引脚之间电连接的一个或多个P-EPI / N +二极管。 一个或多个P-EPI / N +二极管的第一P-EPI / N +二极管包括电连接到第一引脚的阴极。

公开(公告)号：US09184098B2

公开(公告)日：2015-11-10

申请号：US13625577

申请日：2012-09-24

Applicant: ANALOG DEVICES, INC.

Inventor： Javier Alejandro Salcedo ,  Srivatsan Parthasarathy ,  Shuyun Zhang

IPC: H01L29/778 ,  H01L21/8252 ,  H01L27/02 ,  H01L27/06 ,  H01L29/20 ,  H01L29/205

CPC classification number: H01L21/8252 ,  H01L27/0248 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7786

Abstract: A protection circuit including a multi-gate high electron mobility transistor (HEMT), a forward conduction control block, and a reverse conduction control block is provided between a first terminal and a second terminal. The multi-gate HEMT includes an explicit drain/source, a first depletion-mode (D-mode) gate, a first enhancement-mode (E-mode) gate, a second E-mode gate, a second D-mode gate, and an explicit source/drain. The drain/source and the first D-mode gate are connected to the first terminal and the source/drain and the second D-mode gate are connected to the second terminal. The forward conduction control block turns on the second E-mode gate when a voltage difference between the first and second terminals is greater than a forward conduction trigger voltage, and the reverse conduction control block turns on the first E-mode gate when the voltage difference is more negative than a reverse conduction trigger voltage.

Abstract translation: 在第一端子和第二端子之间设置包括多栅极高电子迁移率晶体管（HEMT），正向传导控制块和反向导通控制块的保护电路。 多栅极HEMT包括显式漏极/源极，第一耗尽模式（D模式）栅极，第一增强模式（E模式）栅极，第二E模式栅极，第二D模式栅极， 和明确的源/漏。 漏极/源极和第一D型栅极连接到第一端子，源极/漏极和第二D型栅极连接到第二端子。 当第一和第二端子之间的电压差大于正向传导触发电压时，正向传导控制块导通第二E模式栅极，当反向导通控制模块的电压差 比反向传导触发电压更负。

公开(公告)号：US20150070806A1

公开(公告)日：2015-03-12

申请号：US14024426

申请日：2013-09-11

Applicant: ANALOG DEVICES, INC.

Inventor： Srivatsan Parthasarathy ,  Javier Alejandro Salcedo

IPC: H02H9/04

CPC classification number: H02H9/04 ,  H02H9/046

Abstract: Apparatus and methods for active detection, timing, and protection related to transient electrical events are disclosed. A detection circuit generates a detection signal in response to a transient electrical stress. First and second driver circuits of an integrated circuit, each driver having one or more bipolar junction transistors, activate based on the detection signal and generate activation signals. The one or more bipolar junction transistors of the first and second driver circuits are configured to conduct current substantially laterally across respective base regions. A discharge circuit, having an upper discharge element and a lower discharge element, receives the activation signals and activates to attenuate the transient electrical event.

Abstract translation: 公开了与瞬时电气事件相关的主动检测，定时和保护的装置和方法。 检测电路响应瞬时电应力产生检测信号。 集成电路的第一和第二驱动器电路，具有一个或多个双极结型晶体管的每个驱动器基于检测信号而激活并产生激活信号。 第一和第二驱动器电路的一个或多个双极结型晶体管被配置为基本横向地跨过相应的基极区域传导电流。 具有上放电元件和下放电元件的放电电路接收激活信号并激活以衰减瞬时电事件。

公开(公告)号：US20140332843A1

公开(公告)日：2014-11-13

申请号：US14446205

申请日：2014-07-29

Applicant: Analog Devices, Inc.

Inventor： David J. Clarke ,  Javier Alejandro Salcedo ,  Brian B. Moane ,  Juan Luo ,  Seamus Murnane ,  Kieran K. Heffernan ,  John Twomey ,  Stephen Denis Heffernan ,  Gavin Patrick Cosgrave

IPC: H01L27/02 ,  H01L29/747 ,  H01L29/74 ,  H01L27/06

CPC classification number: H01L27/0248 ,  H01L27/0635 ,  H01L27/0647 ,  H01L29/0692 ,  H01L29/66386 ,  H01L29/7412 ,  H01L29/747

Abstract: Junction-isolated blocking voltage devices and methods of forming the same are provided. In certain implementations, a blocking voltage device includes an anode terminal electrically connected to a first p-well, a cathode terminal electrically connected to a first n-well, a ground terminal electrically connected to a second p-well, and an n-type isolation layer for isolating the first p-well from a p-type substrate. The first p-well and the first n-well operate as a blocking diode. The blocking voltage device further includes a PNPN silicon controlled rectifier (SCR) associated with a P+ region formed in the first n-well, the first n-well, the first p-well, and an N+ region formed in the first p-well. Additionally, the blocking voltage device further includes an NPNPN bidirectional SCR associated with an N+ region formed in the first p-well, the first p-well, the n-type isolation layer, the second p-well, and an N+ region formed in the second p-well.

Abstract translation: 提供了隔离隔离电压装置及其形成方法。 在某些实施方案中，阻断电压装置包括电连接到第一p阱的阳极端子，电连接到第一n阱的阴极端子，电连接到第二p阱的接地端子，以及n型 用于将第一p阱与p型衬底隔离的隔离层。 第一个p阱和第一个n阱作为阻塞二极管工作。 阻断电压装置还包括与形成在第一n阱，第一n阱，第一p阱以及形成在第一p阱中的N +区相关的PN +可控硅整流器（SCR） 。 另外，阻断电压装置还包括与形成在第一p阱，第一p阱，n型隔离层，第二p阱以及形成在第一p阱中的N +区域相关联的N +区域的NPNPN双向SCR 第二个p井。

公开(公告)号：US20130270605A1

公开(公告)日：2013-10-17

申请号：US13913202

申请日：2013-06-07

Applicant: ANALOG DEVICES, INC.

Inventor： Javier Alejandro Salcedo ,  Karl Sweetland

IPC: H01L29/747 ,  H01L29/66

CPC classification number: H01L29/747 ,  H01L27/0262 ,  H01L29/66386

Abstract: An apparatus and method for high voltage transient electrical overstress protection are disclosed. In one embodiment, the apparatus includes an internal circuit electrically connected between a first node and a second node; and a protection circuit electrically connected between the first node and the second node. The protection circuit is configured to protect the internal circuit from transient electrical overstress events while maintaining a relatively high holding voltage upon activation. The holes- or electrons-enhanced conduction protection circuit includes a bi-directional bipolar device having an emitter/collector, a base, and a collector/emitter; a first bipolar transistor having an emitter electrically coupled to the first node, a base electrically coupled to the emitter/collector of the bipolar device, and a collector electrically coupled to the base of the bipolar transistor; and a second bipolar transistor having an emitter electrically coupled to the second node, a base electrically coupled to the collector/emitter of the bipolar device, and a collector electrically coupled to the base of the bipolar transistor.

Abstract translation: 公开了一种用于高压瞬态电过载保护的装置和方法。 在一个实施例中，该装置包括电连接在第一节点和第二节点之间的内部电路; 以及电连接在第一节点和第二节点之间的保护电路。 保护电路被配置为保护内部电路免受瞬态电应力事件的影响，同时在激活时保持相对较高的保持电压。 空穴或电子增强的传导保护电路包括具有发射极/集电极，基极和集电极/发射极的双向双极器件; 第一双极晶体管，其具有电耦合到第一节点的发射极，电耦合到双极器件的发射极/集电极的基极，以及电耦合到双极晶体管的基极的集电极; 以及具有电耦合到第二节点的发射极的第二双极晶体管，电耦合到双极器件的集电极/发射极的基极，以及电耦合到双极晶体管的基极的集电极。

公开(公告)号：US10068894B2

公开(公告)日：2018-09-04

申请号：US14594394

申请日：2015-01-12

Applicant: Analog Devices, Inc.

Inventor： James Zhao ,  Javier Alejandro Salcedo

IPC: H01L27/02 ,  H01L21/8222 ,  H01L49/02 ,  H01L29/06 ,  H01L29/10 ,  H03K17/567 ,  H01L29/861

Abstract: Low leakage bidirectional clamps and methods of forming the same are provided. In certain configurations, a bidirectional clamp includes a first p-well region, a second p-well region, and an n-well region positioned between the first and second p-wells regions. The bidirectional clamp further includes two or more oxide regions over the n-well region, and one or more n-type active (N+) dummy blocking current regions are positioned between the oxide regions. The one or more N+ dummy leakage current blocking regions interrupt an electrical path from the first p-type well region to the second p-type well region along interfaces between the n-well region and the oxide regions. Thus, even when charge accumulates at the interfaces due to extended high voltage, e.g., >60V, and/or high temperature operation (e.g., >125° C.), the N+ dummy leakage current blocking regions inhibit charge trapping-induced leakage current.

公开(公告)号：US10008490B2

公开(公告)日：2018-06-26

申请号：US15614048

申请日：2017-06-05

Applicant: Analog Devices, Inc.

Inventor： Javier Alejandro Salcedo ,  Jonathan Pfeifer

IPC: H01L27/02

CPC classification number: H01L27/0259 ,  H01L27/0207 ,  H01L27/0262

Abstract: The disclosed technology relates to electronics, and more particularly, to protection devices that protect circuits from transient electrical events such as electrical overstress/electrostatic discharge. A protection device includes a semiconductor substrate having formed therein at least two wells and a deep well underlying and contacting the at least two wells. The device additionally includes a first PN diode formed in one of the at least two wells and having a first heavily doped region of a first conductivity type and a first heavily doped region of a second conductivity type, and includes a second PN diode formed in one of the at least two wells and having a second heavily doped region of the first conductivity type and a second heavily doped region of the second conductivity type. The device additionally includes a first PN diode and the second PN diode are electrically shorted by an electrical shorting structure to form a first plurality of serially connected diodes having a threshold voltage. The device further includes a PNPN silicon-controlled rectifier (SCR) having a trigger voltage and comprising the first heavily doped region of the first conductivity type, the at least two wells, the deep well, and the second heavily doped region of the second conductivity type.

公开(公告)号：US20180158814A1

公开(公告)日：2018-06-07

申请号：US15370912

申请日：2016-12-06

Applicant: ANALOG DEVICES, INC.

Inventor： Javier Alejandro Salcedo ,  Srivatsan Parthasarathy

IPC: H01L27/02 ,  H01L23/50 ,  H02H9/04

CPC classification number: H01L27/0285 ,  H01L27/0255 ,  H01L27/0262 ,  H02H9/046

Abstract: In certain configurations, an input/output (IO) interface of a semiconductor chip includes a pin, an interface switch connected to the pin, and an overstress detection and active control circuit that controls a resistance of the interface switch with active feedback. The overstress detection and active control circuit increases a resistance of the interface switch in response to detection of a transient overstress event between a first node and a second node. Accordingly, the overstress detection and active control circuit provides separate detection and logic control to selectively modify the resistance of the interface switch such that the interface switch operates with low resistance during normal operating conditions and with high resistance during overstress conditions.