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    Power saving feature for storage subsystems
    1.
    发明授权
    Power saving feature for storage subsystems 有权

    公开(公告)号：US10089266B2

    公开(公告)日：2018-10-02

    申请号：US14797041

    申请日：2015-07-10

    Applicant: Apple Inc.

    Inventor： Christopher J. Sarcone ,  Manoj K. Radhakrishnan ,  Etai Zaltsman

    IPC: G06F13/26 ,  G06F1/32

    Abstract: Disclosed herein is a technique for maintaining a responsive user interface for a user while preserving battery life of a user device by dynamically determining the interrupt rate/interrupt time at the user device. Based on priority tier information associated with the I/O requests along with the directionality and size of the I/O requests, a determination can be made regarding how the interrupt rate/interrupt time can be adjusted to achieve acceptable user interface (UI) responsiveness and maximum power savings.

    Data recovery in memory having multiple failure modes
    2.
    发明授权
    Data recovery in memory having multiple failure modes 有权

    公开(公告)号：US09996417B2

    公开(公告)日：2018-06-12

    申请号：US15096303

    申请日：2016-04-12

    Applicant: Apple Inc.

    Inventor： Assaf Shappir ,  Etai Zaltsman ,  Guy Ben-Yehuda

    IPC: G06F11/10 ,  G11C29/52

    CPC classification number: G06F11/1072 ,  G06F11/108 ,  G11C29/52

    Abstract: A controller includes an interface and a processor. The interface is configured to communicate with a memory including multiple memory cells organized in at least two sections each including multiple sets of word lines (WLs), wherein in a first failure mode multiple WLs fail in a single section, and in a second failure mode a WL fails in multiple sections. The processor is configured to assign multiple cell-groups of the memory cells to a parity-group, such that (i) no two cell-groups in the parity-group belong to a same WL, and (ii) no two cell-groups in the parity-group belong to adjacent WLs in a same section, and, upon detecting a failure to access a cell-group in the parity-group, due to either the first or second failure modes but not both failure modes occurring simultaneously, to recover the data stored in the cell-group using one or more remaining cell-groups in the parity-group.

    DATA RECOVERY IN MEMORY HAVING MULTIPLE FAILURE MODES
    3.
    发明申请
    DATA RECOVERY IN MEMORY HAVING MULTIPLE FAILURE MODES 有权

    公开(公告)号：US20170293527A1

    公开(公告)日：2017-10-12

    申请号：US15096303

    申请日：2016-04-12

    Applicant: Apple Inc.

    Inventor： Assaf Shappir ,  Etai Zaltsman ,  Guy Ben-Yehuda

    IPC: G06F11/10 ,  G11C29/52

    CPC classification number: G06F11/1072 ,  G06F11/108 ,  G11C29/52

    Abstract: A controller includes an interface and a processor. The interface is configured to communicate with a memory including multiple memory cells organized in at least two sections each including multiple sets of word lines (WLs), wherein in a first failure mode multiple WLs fail in a single section, and in a second failure mode a WL fails in multiple sections. The processor is configured to assign multiple cell-groups of the memory cells to a parity-group, such that (i) no two cell-groups in the parity-group belong to a same WL, and (ii) no two cell-groups in the parity-group belong to adjacent WLs in a same section, and, upon detecting a failure to access a cell-group in the parity-group, due to either the first or second failure modes but not both failure modes occurring simultaneously, to recover the data stored in the cell-group using one or more remaining cell-groups in the parity-group.

    PARALLEL DATA STORAGE IN GROUPS OF MEMORY BLOCKS HAVING SIMILAR PERFORMANCE CHARACTERISTICS
    4.
    发明申请
    PARALLEL DATA STORAGE IN GROUPS OF MEMORY BLOCKS HAVING SIMILAR PERFORMANCE CHARACTERISTICS 审中-公开
    具有类似性能特性的存储器组中的并行数据存储

    公开(公告)号：US20160147444A1

    公开(公告)日：2016-05-26

    申请号：US14551016

    申请日：2014-11-23

    Applicant: Apple Inc.

    Inventor： Moshe Neerman ,  Etai Zaltsman ,  Avraham (Poza) Meir

    IPC: G06F3/06

    CPC classification number: G06F3/061 ,  G06F3/064 ,  G06F3/0644 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688

    Abstract: A method for data storage includes, in a memory that includes multiple memory blocks, assessing a performance characteristic of the multiple memory blocks. At least some of the memory blocks are grouped into groups using a grouping criterion that groups together the memory blocks based on similarity in the assessed performance characteristic. Data is stored in the memory by applying parallel memory access operations in the groups of the memory blocks.

    Abstract translation: 一种用于数据存储的方法包括在包括多个存储块的存储器中，评估多个存储器块的性能特性。 基于评估的性能特征的相似性，使用分组标准将至少一些存储器块分组成组。 通过在存储器块的组中应用并行存储器访问操作来将数据存储在存储器中。

    Memory System with Shared File System
    5.
    发明申请
    Memory System with Shared File System 有权
    具有共享文件系统的内存系统

    公开(公告)号：US20150106410A1

    公开(公告)日：2015-04-16

    申请号：US14050737

    申请日：2013-10-10

    Applicant: Apple Inc.

    Inventor： Etai Zaltsman ,  Sasha Paley ,  Avraham Poza Meir

    IPC: G06F3/06 ,  G06F12/08 ,  G06F17/30

    CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/0658 ,  G06F3/0661 ,  G06F3/0671 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/0253 ,  G06F12/0833 ,  G06F17/30218 ,  G06F2212/621

    Abstract: An apparatus includes a non-volatile memory and a processor. The processor is configured to receive, from a host, commands for storage of data in the non-volatile memory, to further receive from the host, for storage in the non-volatile memory, File System (FS) information that specifies organization of the data in a FS of the host, to receive from the host a directive that grants the processor permission and capability to access and modify the FS information, and to access the FS information, using the directive, so as to manage the storage of the data in the non-volatile memory.

    Abstract translation: 一种装置包括非易失性存储器和处理器。 处理器被配置为从主机接收用于在非易失性存储器中存储数据的命令，以进一步从主机接收用于存储在非易失性存储器中的文件系统（FS）信息，所述文件系统（FS）信息指定 在主机的FS中的数据，从主机接收授权处理器许可和访问和修改FS信息的能力的指令，以及使用该指令访问FS信息，以便管理数据的存储 在非易失性内存中。

    VECTOR CIRCUIT WITH SCALAR OPERATIONS IN ACCELERATOR CIRCUIT FOR MATHEMATICAL OPERATIONS
    6.
    发明公开
    VECTOR CIRCUIT WITH SCALAR OPERATIONS IN ACCELERATOR CIRCUIT FOR MATHEMATICAL OPERATIONS 审中-公开

    公开(公告)号：US20230267168A1

    公开(公告)日：2023-08-24

    申请号：US17675369

    申请日：2022-02-18

    Applicant: Apple Inc.

    Inventor： Liran Fishel ,  Danny Gal ,  Nir Nissan ,  Etai Zaltsman

    IPC: G06F17/16

    CPC classification number: G06F17/16

    Abstract: Embodiments of the present disclosure relate to a vector circuit in an accelerator circuit for performing vector and scalar operations. The vector circuit reads a subset of instructions from an instruction memory, each instruction including an identification of at least a portion of a first vector and an identification of at least a portion of a second vector. The vector circuit further receives a portion of input data from a data memory corresponding to the subset of instructions. The vector circuit performs a respective operation in accordance with each instruction on at least one first element of the first vector and at least one second element of the second vector to generate at least one output element of an output vector. Each instruction indicates positions in respective vectors for the at least one first element, the at least one second element and the at least one output element.

    Memory system with shared file system
    7.
    发明授权
    Memory system with shared file system 有权
    具有共享文件系统的内存系统

    公开(公告)号：US09535628B2

    公开(公告)日：2017-01-03

    申请号：US14050737

    申请日：2013-10-10

    Applicant: Apple Inc.

    Inventor： Etai Zaltsman ,  Sasha Paley ,  Avraham Poza Meir

    IPC: G06F12/02 ,  G06F3/06 ,  G06F17/30 ,  G06F12/08

    CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/0658 ,  G06F3/0661 ,  G06F3/0671 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/0253 ,  G06F12/0833 ,  G06F17/30218 ,  G06F2212/621

    Abstract: An apparatus includes a non-volatile memory and a processor. The processor is configured to receive, from a host, commands for storage of data in the non-volatile memory, to further receive from the host, for storage in the non-volatile memory, File System (FS) information that specifies organization of the data in a FS of the host, to receive from the host a directive that grants the processor permission and capability to access and modify the FS information, and to access the FS information, using the directive, so as to manage the storage of the data in the non-volatile memory.

    Abstract translation: 一种装置包括非易失性存储器和处理器。 处理器被配置为从主机接收用于在非易失性存储器中存储数据的命令，以进一步从主机接收用于存储在非易失性存储器中的文件系统（FS）信息，所述文件系统（FS）信息指定 在主机的FS中的数据，从主机接收授权处理器许可和访问和修改FS信息的能力的指令，以及使用该指令访问FS信息，以便管理数据的存储 在非易失性存储器中。

    Redundancy schemes for non-volatile memory using parity zones having new and old parity blocks
    9.
    发明授权
    Redundancy schemes for non-volatile memory using parity zones having new and old parity blocks 有权
    使用具有新旧奇偶校验块的奇偶校验区的非易失性存储器的冗余方案

    公开(公告)号：US08914670B2

    公开(公告)日：2014-12-16

    申请号：US13670604

    申请日：2012-11-07

    Applicant: Apple Inc.

    Inventor： Etai Zaltsman ,  Julian Vlaiko ,  Ori Moshe Stern ,  Avraham Poza Meir

    IPC: G06F11/00

    CPC classification number: G06F11/108

    Abstract: A method includes, in a non-volatile memory that includes multiple memory blocks, defining a redundancy zone that includes at least an old parity block, a new parity block and multiple active blocks of which one block is defined as an open block. Data is stored in the redundancy zone and the stored data is protected, such that new input data is stored in the open block, redundancy information for the active blocks including the open block is stored in the new parity block, and the redundancy information for the active blocks excluding the open block is stored in the old parity block. Upon filling the open block and the new parity block, an alternative block is assigned to serve as the open block and the new parity block is assigned to serve as the old parity block.

    Abstract translation: 一种方法包括在包括多个存储器块的非易失性存储器中，定义包括至少一个旧奇偶校验块，新奇偶校验块和多个活动块的冗余区，其中一个块被定义为开放块。 将数据存储在冗余区域中，并且存储的数据被保护，使得新的输入数据被存储在开放块中，用于包括打开块的活动块的冗余信息被存储在新的奇偶校验块中，并且冗余信息用于 不包括打开块的活动块存储在旧的奇偶校验块中。 在填充开放块和新的奇偶校验块时，分配替代块用作开放块，并且新的奇偶校验块被分配用作旧的奇偶校验块。

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