ISOLATION MODULE FOR BACKSIDE POWER DELIVERY

    公开(公告)号:US20250063797A1

    公开(公告)日:2025-02-20

    申请号:US18762053

    申请日:2024-07-02

    Abstract: A method of forming a portion of a gate-all-around field-effect transistor includes performing a selective deposition process to form selective cap layers at bottoms of contact trenches formed within portions of a substrate isolated by shallow trench isolations (STIs), wherein the contact trenches each interface with an S/D epitaxial (epi) layer with an extension region, performing a substrate angled etch process to etch sidewalls of the contact trenches, enlarging top critical dimension (CD) of the contact trenches, performing a substrate selective removal plasma (SRP) etch process to isotropically etch the substrate within the contact trenches, performing a recess fill process to fill the contact trenches with dielectric layers, performing an inter-layer dielectric (ILD) recess process to partially remove the substrate between the dielectric layers within the contact trenches and form an ILD recess, and performing a substrate isotropic etch process to partially remove the substrate within the ILD recess.

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