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    Technique for controlling stashing of data
    1.
    发明授权
    Technique for controlling stashing of data 有权

    公开(公告)号：US12001722B2

    公开(公告)日：2024-06-04

    申请号：US17890456

    申请日：2022-08-18

    申请人： Arm Limited

    发明人： Pavel Shamis ,  Honnappa Nagarahalli ,  Jamshed Jalal

    IPC分类号： G06F3/06

    CPC分类号： G06F3/0659 ,  G06F3/0604 ,  G06F3/0635 ,  G06F3/0673

    摘要： There is provided an apparatus, method, and computer-readable medium. The apparatus comprises interconnect circuitry to couple a device to one or more processing elements and to one or more storage structures. The apparatus also comprises stashing circuitry configured to receive stashing transactions from the device, each stashing transaction comprising payload data and control data. The stashing circuitry is responsive to a given stashing transaction whose control data identifies a plurality of portions of the payload data, to perform a plurality of independent stashing decision operations, each of the plurality of independent stashing decision operations corresponding to a respective portion of the plurality of portions of payload data and comprising determining, with reference to the control data, whether to direct the respective portion to one of the one or more storage structures or whether to forward the respective portion to memory.

    Write operation status
    2.
    发明授权
    Write operation status 有权

    公开(公告)号：US11593025B2

    公开(公告)日：2023-02-28

    申请号：US16743409

    申请日：2020-01-15

    申请人： Arm Limited

    发明人： Gurunath Ramagiri ,  Jamshed Jalal ,  Mark David Werkheiser ,  Tushar P Ringe ,  Klas Magnus Bruce ,  Ritukar Khanna

    IPC分类号： G06F3/06

    摘要： A request node is provided comprising request circuitry to issue write requests to write data to storage circuitry. The write requests are issued to the storage circuitry via a coherency node. Status receiving circuitry receives a write status regarding write operations at the storage circuitry from the coherency node and throttle circuitry throttles a rate at which the write requests are issued to the storage circuitry in dependence on the write status. A coherency node is also provided, comprising access circuitry to receive a write request from a request node to write data to storage circuitry and to access the storage circuitry to write the data to the storage circuitry. Receive circuitry receives, from the storage circuitry, an incoming write status regarding write operations at the storage circuitry and transmit circuitry transmits an outgoing write status to the request node based on the incoming write status.

    Configurable cache coherency controller
    3.
    发明授权
    Configurable cache coherency controller 有权

    公开(公告)号：US11550720B2

    公开(公告)日：2023-01-10

    申请号：US17102997

    申请日：2020-11-24

    申请人： Arm Limited

    发明人： Gurunath Ramagiri ,  Jamshed Jalal ,  Mark David Werkheiser ,  Tushar P Ringe ,  Mukesh Patel ,  Sakshi Verma

    IPC分类号： G06F12/0815 ,  G06F12/0831

    摘要： Entries in a cluster-to-caching agent map table of a data processing network identify one or more caching agents in a caching agent cluster. A snoop filter cache stores coherency information that includes coherency status information and a presence vector, where a bit position in the presence vector is associated with a caching agent cluster in the cluster-to-caching agent map table. In response to a data request, a presence vector in the snoop filter cache is accessed to identify a caching agent cluster and the map table is accessed to identify target caching agents for snoop messages. In order to reduce message traffic, snoop message are sent only to the identified targets.

    Distributed virtual memory management for data processing network
    4.
    发明授权
    Distributed virtual memory management for data processing network 有权

    公开(公告)号：US11531620B2

    公开(公告)日：2022-12-20

    申请号：US17212804

    申请日：2021-03-25

    申请人： Arm Limited

    发明人： Kishore Kumar Jagadeesha ,  Jamshed Jalal ,  Tushar P Ringe ,  Mark David Werkheiser ,  Premkishore Shivakumar ,  Lauren Elise Guckert

    IPC分类号： G06F12/0815 ,  G06F12/0831 ,  G06F13/40

    摘要： A data processing network includes request nodes with local memories accessible as a distributed virtual memory (DVM) and coupled by an interconnect fabric. Multiple DVM domains are assigned, each containing a DVM node for handling DVM operation requests from request nodes in the domain. On receipt of a request, a DVM node sends a snoop message to other request nodes in its domain and sends a snoop message to one or more peer DVM nodes in other DVM domains. The DVM node receives snoop responses from the request nodes and from the one or more peer DVM nodes, and send a completion message to the first request node. Each peer DVM node sends snoop messages to the request nodes in its domain, collects snoop responses, and sends a single response to the originating DVM node. In this way, DVM operations are performed in parallel.

    Writing zero data
    6.
    发明授权
    Writing zero data 有权

    公开(公告)号：US11188377B2

    公开(公告)日：2021-11-30

    申请号：US16592979

    申请日：2019-10-04

    申请人： Arm Limited

    发明人： Jamshed Jalal ,  Mark David Werkheiser ,  Phanindra Kumar Mannava ,  Bruce James Mathewson

    IPC分类号： G06F12/0891 ,  G06F12/0808 ,  G06F9/46 ,  G06F9/455 ,  G06F13/40 ,  G06F12/10 ,  G06F9/38

    摘要： Apparatuses, methods of operating apparatuses, interconnects for connecting apparatuses to one another, and methods of operating the interconnects are disclosed. A master apparatus can issue an individual all-zero-data write transaction specifying a data storage location to the interconnect, which conveys the individual all-zero-data write transaction to a target device which writes all-zero-data at the data storage location. No write data is conveyed with the individual all-zero-data write transaction, so that the individual all-zero-data write transaction may be used to clear the data storage location without adding to congestion of a write data channel in the interconnect.

    Forwarding responses to snoop requests
    7.
    发明授权
    Forwarding responses to snoop requests 有权

    公开(公告)号：US11159636B2

    公开(公告)日：2021-10-26

    申请号：US15427384

    申请日：2017-02-08

    申请人： ARM Limited

    发明人： Phanindra Kumar Mannava ,  Bruce James Mathewson ,  Jamshed Jalal ,  Klas Magnus Bruce

    IPC分类号： H04L29/08 ,  G06F12/0831

    摘要： A data processing apparatus is provided, which includes receiving circuitry to receive a snoop request in respect of requested data on behalf of a requesting node. The snoop request includes an indication as to whether forwarding is to occur. Transmitting circuitry transmits a response to the snoop request and cache circuitry caches at least one data value. When forwarding is to occur and the at least one data value includes the requested data, the response includes the requested data and the transmitting circuitry transmits the response to the requesting node.

    Read transaction tracker lifetimes in a coherent interconnect system
    8.
    发明授权
    Read transaction tracker lifetimes in a coherent interconnect system 有权

    公开(公告)号：US10795820B2

    公开(公告)日：2020-10-06

    申请号：US15427435

    申请日：2017-02-08

    申请人： ARM Limited

    发明人： Phanindra Kumar Mannava ,  Bruce James Mathewson ,  Jamshed Jalal ,  Tushar P Ringe

    IPC分类号： G06F12/0831 ,  G06F11/14

    摘要： Apparatus and a corresponding method of operating the apparatus, in a coherent interconnect system comprising a requesting master device and a data-storing slave device, are provided. The apparatus maintains records of coherency protocol transactions received from the requesting master device whilst completion of the coherency protocol transactions are pending and is responsive to reception of a read transaction from the requesting master device for a data item stored in the data-storing slave device to issue a direct memory transfer request to the data-storing slave device. A read acknowledgement trigger is added to the direct memory transfer request and in response to reception of a read acknowledgement signal from the data-storing slave device a record created by reception of the read transaction is updated corresponding to completion of the direct memory transfer request. The lifetime that the apparatus needs to maintain the record is thus reduced, despite the read transaction being satisfied by a direct memory transfer. A corresponding data-storing slave device and method of operating the data-storing slave device are also provided.

    Cache maintenance operations in a data processing system
    9.
    发明授权
    Cache maintenance operations in a data processing system 有权

    公开(公告)号：US10783080B2

    公开(公告)日：2020-09-22

    申请号：US16173213

    申请日：2018-10-29

    申请人： Arm Limited

    发明人： Phanindra Kumar Mannava ,  Bruce James Mathewson ,  Jamshed Jalal ,  Paul Gilbert Meyer

    IPC分类号： G06F12/08 ,  G06F12/0868 ,  G06F12/0871 ,  G06F12/1009 ,  G06F3/06 ,  G06F9/52

    摘要： An interconnect system and method of operating the system are disclosed. A master device has access to a cache and a slave device has an associated data storage device for long-term storage of data items. The master device can initiate a cache maintenance operation in the interconnect system with respect to a data item temporarily stored in the cache causing action to be taken by the slave device with respect to storage of the data item in the data storage device. For long latency operations the master device can issue a separated cache maintenance request specifying the data item and the slave device. In response an intermediate device signals an acknowledgment response indicating that it has taken on responsibility for completion of the cache maintenance operation and issues the separated cache maintenance request to the slave device. The slave device signals the acknowledgement response to the intermediate device and on completion of the cache maintenance operation with respect to the data item stored in the data storage device signals a completion response to the master device.