公开(公告)号：US20210064528A1

公开(公告)日：2021-03-04

申请号：US16550607

申请日：2019-08-26

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  Matthew Andrew RAFACZ ,  Guillaume BOLBENES ,  Houdhaifa BOUZGUARROU ,  . ABHISHEK RAJA

IPC: G06F12/0808 ,  G06F12/1027

Abstract: A data processing apparatus is provided. Cache circuitry caches data, the data being indexed according to execution contexts of processing circuitry. Receive circuitry receives invalidation requests each referencing a specific execution context in the execution contexts. Invalidation circuitry invalidates at least some of the data in the cache circuitry and filter circuitry filters the invalidation requests based on at least one condition and, when the condition is met, causes the invalidation circuitry to invalidate the data in the cache circuitry.

公开(公告)号：US20180253387A1

公开(公告)日：2018-09-06

申请号：US15446235

申请日：2017-03-01

Applicant: ARM Limited

Inventor： Huzefa Moiz SANJELIWALA ,  Klas Magnus BRUCE ,  Leigang KOU ,  Michael FILIPPO ,  Miles Robert DOOLEY ,  Matthew Andrew RAFACZ

IPC: G06F12/12 ,  G06F12/0897

CPC classification number: G06F12/0897 ,  G06F12/0862 ,  G06F2212/1028 ,  G06F2212/1041 ,  G06F2212/60

Abstract: A data processing apparatus is provided that includes a plurality of storage elements. Receiving circuitry receives a plurality of incoming data beats from cache circuitry and stores the incoming data beats in the storage elements. At least one existing data beat in the storage elements is replaced by an equal number of the incoming data beats belonging to a different cache line of the cache circuitry. The existing data beats stored in said plurality of storage elements form an incomplete cache line.

公开(公告)号：US20210026770A1

公开(公告)日：2021-01-28

申请号：US16520657

申请日：2019-07-24

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  Matthew Andrew RAFACZ

IPC: G06F12/0815 ,  G06F12/0875 ,  G06F12/0808 ,  G06F12/1018 ,  G06F9/38

Abstract: A data processing apparatus is provided, which includes a cache to store operations produced by decoding instructions fetched from memory. The cache is indexed by virtual addresses of the instructions in the memory. Receiving circuitry receives an incoming invalidation request that references a physical address in the memory. Invalidation circuitry invalidates entries in the cache where the virtual address corresponds with the physical address. Coherency is thereby achieved when using a cache that is indexed using virtual addresses.

公开(公告)号：US20180095893A1

公开(公告)日：2018-04-05

申请号：US15281502

申请日：2016-09-30

Applicant: ARM LIMITED

Inventor： Miles Robert DOOLEY ,  Matthew Andrew RAFACZ ,  Huzefa Moiz SANJELIWALA ,  Michael FILIPPO

IPC: G06F12/1045 ,  G06F12/0862 ,  G06F12/0897

CPC classification number: G06F12/1045 ,  G06F9/30 ,  G06F9/3016 ,  G06F12/0862 ,  G06F12/0897 ,  G06F2212/1016 ,  G06F2212/50 ,  G06F2212/602

Abstract: A data processing apparatus is provided including queue circuitry to respond to control signals each associated with a memory access instruction, and to queue a plurality of requests for data, each associated with a reference to a storage location. Resolution circuitry acquires a request for data, and issues the request for data, the resolution circuitry having a resolution circuitry limit. When a current capacity of the resolution circuitry is below the resolution circuitry limit, the resolution circuitry acquires the request for data by receiving the request for data from the queue circuitry, stores the request for data in association with the storage location, issues the request for data, and causes a result of issuing the request for data to be provided to said storage location. When the current capacity of the resolution circuitry meets or exceeds the resolution circuitry limit, the resolution circuitry acquires the request for data by examining a next request for data in the queue circuitry and issues a further request for the data based on the request for data.