公开(公告)号：US11579920B2

公开(公告)日：2023-02-14

申请号：US16934355

申请日：2020-07-21

Applicant: Arm Limited

Inventor： Timothy Nicholas Hay ,  Nathan William Whitaker ,  Haralds Capkevics

IPC: G06F9/48 ,  G06F9/455 ,  G06F9/50

Abstract: An apparatus comprises an interrupt distributor to distribute virtual interrupts to one or more physical processors, each virtual interrupt to be handled by one of a plurality of virtual processors mappable to said one or more physical processors; and control circuitry to maintain virtual processor interrupt tracking information corresponding to a given virtual processor. The virtual processor interrupt tracking information includes a pending interrupt record tracking which types of virtual interrupts are pending for the given virtual processor, and separate from the pending interrupt record, a pending interrupt status indication indicating a pending interrupt status for the given virtual processor. The pending interrupt status indicates whether the number of pending virtual interrupts for the given virtual processor is zero.

公开(公告)号：US11429426B2

公开(公告)日：2022-08-30

申请号：US17056896

申请日：2019-05-01

Applicant: Arm Limited

Inventor： Timothy Nicholas Hay ,  Martin Weidmann ,  Michael Alexander Kennedy ,  Andrew John Turner

IPC: G06F9/48 ,  G06F9/455 ,  G06F9/52 ,  G06F9/54

Abstract: An interrupt controller comprises issue circuitry to issue interrupt requests to a processing element and control circuitry to detect presence of a race condition in association with at least one pending interrupt request to be issued, and to set a barrier indicator when the race condition has been resolved. In response to the race condition being present, the issue circuitry is configured to select one of the at least one pending interrupt requests, to issue to the processing element the selected pending interrupt request followed by a dummy request over a path that ensures that the processing element receives the selected pending interrupt request prior to receiving the dummy request. On receiving an acknowledgement indicating that the processing element has received the dummy request, the control circuitry is then configured to set the barrier indicator.

公开(公告)号：US10545893B1

公开(公告)日：2020-01-28

申请号：US16245337

申请日：2019-01-11

Applicant: Arm Limited

Inventor： Zheng Xu ,  Abdul Ghani Kanawati ,  Timothy Nicholas Hay

IPC: G06F13/26 ,  G06F11/16 ,  G06F15/17 ,  G06F11/20

Abstract: An interrupt controller, and method of operation of such an interrupt controller, are provided. The interrupt controller has an interrupt source interface for receiving interrupts from one or more interrupt sources, and a plurality of output interfaces, where each output interface is associated with a processing device that can execute an interrupt service routine to process an interrupt request issued to that processing device. The interrupt source interface has transaction generation circuitry to generate, for each received interrupt, an original transaction to represent the interrupt and a duplicate transaction to represent the interrupt. Buffer circuitry then buffers the original transaction and the duplicate transaction for each received interrupt, and selection circuitry is provided for selecting transactions from the buffer circuitry, and for routing each selected transaction for receipt by the output interface identified by an address portion of the selected transaction. Each output interface has queue storage comprising a plurality of queue entries, where each queue entry is allocated to a transaction received by the output interface and is used to store interrupt identifying information provided by a data portion of the transaction. The queue storage is arranged to maintain duplication tracking information to identify when both the original transaction and its associated duplicate transaction have been received by the output interface. Each output interface inhibits issuing an output signal that would cause an interrupt request for the original transaction to be sent to the associated processing device, until the duplication tracking information identifies that both the original transaction and the associated duplicate transaction have been received by that output interface. This provides an efficient functional safety compliant design for an interrupt controller.

公开(公告)号：US20240089042A1

公开(公告)日：2024-03-14

申请号：US18459625

申请日：2023-09-01

Applicant: Arm Limited

Inventor： Haralds Capkevics ,  Timothy Nicholas Hay

IPC: H04L5/00 ,  H04L49/90

CPC classification number: H04L5/0044 ,  H04L49/90

Abstract: Data communication apparatus comprises a receiver comprising message receiver circuitry to receive payload messages and sender control messages from message sender circuitry, the message receiver circuitry comprising: communication circuitry to send receiver control messages to the message sender circuitry, the receiver control messages relating to actions by the message receiver circuitry in response to payload messages or sender control messages from the message sender circuitry; in which the communication circuitry is configured to selectively associate a respective indication with at least some of the receiver control messages sent to the message sender circuitry, the indication indicating whether a given receiver control message with which the indication is associated is a first receiver control message sent by the communication circuitry to the message sender circuitry after a reset of circuitry in the receiver.

公开(公告)号：US20250086128A1

公开(公告)日：2025-03-13

申请号：US18820657

申请日：2024-08-30

Applicant: Arm Limited

Inventor： Timothy Nicholas Hay ,  Endre Papp ,  Richard Anthony Lane ,  Pedro Ochsendorf Portugal

IPC: G06F13/24

Abstract: An apparatus comprises a plurality of interfaces, each couplable to a respective one of a plurality of processing circuitries either in a higher criticality compliance state or a lower criticality compliance state. Each interface can receive from its respective processing circuitry interrupt signals destined to a target processing circuitry of the plurality of processing circuitries and transmit to its respective processing circuitry interrupt signals issued by a source processing circuitry of the plurality of processing circuitries. Control circuitry monitors the flow of the interrupt signals and determines whether the flow of interrupt signals exhibits a discrepancy with respect to an expected flow of interrupt signals, and performs a mitigation action in respect of said discrepancy to avoid violation of the higher criticality compliance state.

公开(公告)号：US11327786B2

公开(公告)日：2022-05-10

申请号：US16934353

申请日：2020-07-21

Applicant: Arm Limited

Inventor： Timothy Nicholas Hay ,  Haralds Capkevics

IPC: G06F9/48 ,  G06F9/455 ,  G06F9/50 ,  G06F13/24

Abstract: Virtual processors are mappable to a number of physical processors. An interrupt distributor is responsible for distributing interrupt requests to a subset of the physical processors. An interface communicates with further interrupt distributors responsible for other physical processors. In response to an interrupt request to be handled by a target virtual processor, the interrupt distributor determines, based on cached virtual processor mapping information, whether to route the interrupt request to one of the subset of physical processors or to one of the further interrupt distributors. When a rejection response is received in response to an interrupt request routed to one of the further interrupt distributors, an update of the cached virtual processing mapping information is requested based on shared virtual processor mapping information, and a resent interrupt request is sent to a further interrupt distributor determined based on the shared virtual processor mapping information.

公开(公告)号：US11593159B2

公开(公告)日：2023-02-28

申请号：US16977580

申请日：2019-02-28

Applicant: ARM LIMITED

Inventor： Martin Weidmann ,  Timothy Nicholas Hay ,  Marc Zyngier

IPC: G06F9/48 ,  G06F9/455 ,  G06F9/50

Abstract: There is provided a data processing apparatus that includes processing circuitry for executing instructions relating to an active virtual processor in a plurality of virtual processors. Exception control circuitry receives an external exception associated with a target virtual processor in the plurality of virtual processors and when the target virtual processor is other than the active virtual processor, it issues a doorbell exception to cause a scheduling operation to schedule the target virtual processor to be the active virtual processor. Storage circuitry stores an indication of a set of masked virtual processors and the scheduling operation is adapted to disregard doorbell exceptions in respect of the set of masked virtual processors.

公开(公告)号：US08935592B2

公开(公告)日：2015-01-13

申请号：US13681789

申请日：2012-11-20

Applicant: ARM Limited

Inventor： Michael Andrew Campbell ,  Timothy Nicholas Hay

IPC: G11C29/00 ,  G06F11/10

CPC classification number: G06F11/10 ,  G06F11/1048

Abstract: An apparatus and method for correcting errors in data accessed from a memory device. A plurality of read symbols are read from a memory device. Syndrome information is then determined from the n data symbols and associated m error correction code symbols. Error correction circuitry uses the syndrome information in order to attempt to locate each read symbol containing an error and to correct the errors in each of those located read symbols. Error tracking circuitry tracks which memory regions the located read symbols containing an error originate from, and, on detecting an error threshold condition, sets at least one memory region as an erasure memory region. The correction circuitry treats each read symbol as a located read symbol containing an error, such that the read symbols to be located are not all randomly distributed and more than PMAX read symbols containing errors can be corrected.

Abstract translation: 一种用于校正从存储器件访问的数据中的错误的装置和方法。 从存储器件读取多个读取符号。 然后从n个数据符号和相关联的m个纠错码符号确定综合征信息。 错误校正电路使用校正子信息来尝试定位包含错误的每个读取符号，并纠正每个读取符号中的每个错误。 错误跟踪电路跟踪哪个存储器区域包含错误的位置的读取符号，并且在检测到错误阈值条件时，将至少一个存储器区域设置为擦除存储器区域。 校正电路将每个读取符号视为包含错误的位置读符号，使得要被定位的读符号不是全部随机分布，并且可以校正多于包含错误的PMAX读符号。

公开(公告)号：US08898430B2

公开(公告)日：2014-11-25

申请号：US13705316

申请日：2012-12-05

Applicant: ARM Limited

Inventor： Viswanath Chakrala ,  Timothy Nicholas Hay ,  Stuart David Biles

IPC: G06F12/10 ,  G06F12/08

CPC classification number: G06F12/0891 ,  G06F11/073 ,  G06F11/0793

Abstract: A data processing apparatus having a memory configured to store tables having virtual to physical address translations, a cache configured to store a subset of the virtual to physical address translations and cache management circuitry configured to control transactions received from the processor requesting virtual address to physical address translations. The data processing apparatus identifies where a faulting transaction has occurred during execution of a context and whether the faulting transaction has a transaction stall or transaction terminate fault. The cache management circuitry is responsive to identification of the faulting transaction having a transaction terminate fault to invalidate all address translations in the cache that relate to the context of the faulting transaction such that a valid bit associated with each entry in the cache is set to invalid for the address translations.

Abstract translation: 一种具有被配置为存储具有虚拟到物理地址转换的表的存储器的数据处理装置，被配置为存储虚拟到物理地址转换的子集的高速缓存以及被配置为控制从处理器接收到的处理器请求虚拟地址到物理地址的高速缓存管理电路 翻译。 数据处理装置识别在执行上下文期间发生故障事务的位置，以及故障事务是否具有事务处理或事务终止故障。 高速缓存管理电路响应于具有事务终止故障的故障事务的识别，以使与高速缓存中的上下文相关的高速缓存中的所有地址转换无效，使得与高速缓存中的每个条目相关联的有效位被设置为无效 为地址翻译。

公开(公告)号：US20140156949A1

公开(公告)日：2014-06-05

申请号：US13705316

申请日：2012-12-05

Applicant: ARM LIMITED

Inventor： Viswanath CHAKRALA ,  Timothy Nicholas Hay ,  Stuart David Biles

IPC: G06F12/08

CPC classification number: G06F12/0891 ,  G06F11/073 ,  G06F11/0793

Abstract: A data processing apparatus having a memory configured to store tables having virtual to physical address translations, a cache configured to store a subset of the virtual to physical address translations and cache management circuitry configured to control transactions received from the processor requesting virtual address to physical address translations. The data processing apparatus identifies where a faulting transaction has occurred during execution of a context and whether the faulting transaction has a transaction stall or transaction terminate fault. The cache management circuitry is responsive to identification of the faulting transaction having a transaction terminate fault to invalidate all address translations in the cache that relate to the context of the faulting transaction such that a valid bit associated with each entry in the cache is set to invalid for the address translations.

Abstract translation: 一种具有被配置为存储具有虚拟到物理地址转换的表的存储器的数据处理装置，被配置为存储虚拟到物理地址转换的子集的高速缓存以及被配置为控制从处理器接收到的处理器请求虚拟地址到物理地址的高速缓存管理电路 翻译。 数据处理装置识别在执行上下文期间发生故障事务的位置，以及故障事务是否具有事务处理或事务终止故障。 高速缓存管理电路响应于具有事务终止故障的故障事务的识别，以使与高速缓存中的上下文相关的高速缓存中的所有地址转换无效，使得与高速缓存中的每个条目相关联的有效位被设置为无效 为地址翻译。