公开(公告)号：US20190007043A1

公开(公告)日：2019-01-03

申请号：US15636428

申请日：2017-06-28

Applicant: ARM Limited

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Yicong Li ,  Hsin-Yu Chen ,  Sriram Thyagarajan

IPC: H03K17/687 ,  G11C5/14 ,  G11C8/08 ,  G11C7/10 ,  G06F17/50 ,  H01L23/64

Abstract: A method to generate a circuit instance to include a plurality of pMOSFET instances, where each pMOSFET instance has a source terminal instance connected to one or more supply rail instances. The circuit instance includes impedance element instances, where each impedance element instance is connected to a source terminal instance and a drain terminal instance of a corresponding pMOSFET instance. Depending upon a set of requirements, one or more of the impedance element instances are in a high impedance state or a low impedance state.

公开(公告)号：US11005461B2

公开(公告)日：2021-05-11

申请号：US16004009

申请日：2018-06-08

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Sai Sriharsha Manapragada ,  Yicong Li ,  Yew Keong Chong ,  Bikas Maiti ,  Sanjay Mangal ,  Hsin-Yu Chen

IPC: H03K3/356 ,  H03K17/22

Abstract: Various implementations described herein are directed to an integrated circuit having first devices arranged to operate as a latch. The first devices may include inner devices and outer devices. The integrated circuit may include second devices coupled to the first devices and arranged to operate as a level shifter. The second devices may include upper devices and lower devices. The lower devices may be cross-coupled to gates of the inner devices and the upper devices. The integrated circuit may include input signals applied to gates of the outer devices and the lower devices to thereby generate output signals from the outputs of the lower devices that are applied to the gates of the inner devices and the upper devices to activate latching of the output signals.

公开(公告)号：US10177760B1

公开(公告)日：2019-01-08

申请号：US15636428

申请日：2017-06-28

Applicant: ARM Limited

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Yicong Li ,  Hsin-Yu Chen ,  Sriram Thyagarajan

IPC: G11C5/06 ,  H03K17/687 ,  G11C5/14 ,  H01L23/64 ,  G11C7/10 ,  G06F17/50 ,  G11C8/08

Abstract: A method to generate a circuit instance to include a plurality of pMOSFET instances, where each pMOSFET instance has a source terminal instance connected to one or more supply rail instances. The circuit instance includes impedance element instances, where each impedance element instance is connected to a source terminal instance and a drain terminal instance of a corresponding pMOSFET instance. Depending upon a set of requirements, one or more of the impedance element instances are in a high impedance state or a low impedance state.

公开(公告)号：US20190244656A1

公开(公告)日：2019-08-08

申请号：US15891212

申请日：2018-02-07

Applicant: Arm Limited

Inventor： Yicong Li ,  Andy Wangkun Chen ,  Sharryl Renee Dettmer ,  Lalit Gupta ,  Jitendra Dasani ,  Yeon Jun Park ,  Shri Sagar Dwivedi ,  Fakhruddin Ali Bohra

IPC: G11C11/4097 ,  G11C7/18 ,  G11C11/419 ,  H01L27/11

Abstract: Various implementations described herein refer to an integrated circuit having memory circuitry. The memory circuitry may include a first array of bitcells accessible with a first bitline pair and a second array of bitcells accessible with a second bitline pair. The integrated circuit may include first transition coupling circuitry for accessing jumper bitline pairs and coupling the jumper bitline pairs to column multiplexer circuitry. The integrated circuit may include second transition coupling circuitry for accessing the first array of bitcells or the second array of bitcells and providing a data output signal to the jumper bitline pairs. The first bitline pair and the second bitline pair may be on a lower metal layer, and the jumper bitline pairs may be on a higher metal layer.