公开(公告)号：US20230265582A1

公开(公告)日：2023-08-24

申请号：US18110403

申请日：2023-02-16

Applicant: ASM IP Holding B.V.

Inventor： Gregory Deye ,  Yen Chun Fu ,  Arun Murali

IPC: C30B33/08 ,  C30B25/18 ,  C30B29/06

CPC classification number: C30B33/08 ,  C30B25/186 ,  C30B29/06

Abstract: A method of processing a surface of an epitaxially grown silicon film includes using a radical species to remove random surface terminations from the surface of the epitaxially grown silicon film and to generate a substantially uniform distribution of surface terminations. Reaction systems for performing such a method, and epitaxially grown films prepared using such a method, also are provided.

公开(公告)号：US20240355688A1

公开(公告)日：2024-10-24

申请号：US18642877

申请日：2024-04-23

Applicant: ASM IP Holding B.V.

Inventor： Amir Kajbafvala ,  Arun Murali ,  Caleb Miskin

IPC: H01L21/66 ,  C23C16/02 ,  C23C16/455 ,  C23C16/46 ,  C23C16/50 ,  C23C16/52 ,  H01L21/67

CPC classification number: H01L22/20 ,  C23C16/0209 ,  C23C16/0227 ,  C23C16/45544 ,  C23C16/46 ,  C23C16/50 ,  C23C16/52 ,  H01L21/67248

Abstract: A method for removing contaminants from an upper surface of a substrate inside various chambers of a semiconductor processing system is provided. The method may comprise heating at least a portion of the upper surface to a predetermined upper surface bake temperature to induce a chemical reaction of the contaminants with hydrogen gas in the deposition chamber and remove contaminants from the upper surface. The temperature of the bulk material forming the substrate remains substantially lower than the predetermined upper surface bake temperature. After heating the upper surface to remove the contaminants, a material layer may be deposited onto the upper surface. The semiconductor processing system and computer instructions for operating the semiconductor processing system are also described.

公开(公告)号：US20230125884A1

公开(公告)日：2023-04-27

申请号：US18048145

申请日：2022-10-20

Applicant: ASM IP Holding, B.V.

Inventor： Gregory Deye ,  Arun Murali ,  Frederick Aryeetey ,  Caleb Miskin ,  Alexandros Demos

IPC: H01L21/02 ,  H01L21/285 ,  H01L21/67 ,  H01L21/687

Abstract: A material layer deposition method includes supporting a substrate in a preclean module and exposing the substrate to a preclean etchant while supported within the preclean module. The substrate is transferred to a deposition module and exposed to an adsorbate while supported within the deposition module. A material layer is the deposited onto the substrate while supported within the deposition module subsequent to exposing the substrate to the adsorbate. Semiconductor processing systems and computer program products are also described.

公开(公告)号：US20240068103A1

公开(公告)日：2024-02-29

申请号：US18458101

申请日：2023-08-29

Applicant: ASM IP Holding, B.V.

Inventor： Yanfu Lu ,  Caleb Miskin ,  Alexandros Demos ,  Amir Kajbafvala ,  Arun Murali

IPC: C23C16/52 ,  C23C16/30 ,  C23C16/458 ,  C23C16/46

CPC classification number: C23C16/52 ,  C23C16/30 ,  C23C16/4584 ,  C23C16/46 ,  G01K7/04

Abstract: A chamber arrangement has a chamber body with upper and lower walls. A substrate support is arranged within an interior of the chamber body and supported for rotation about a rotation axis. An upper heater element array is supported above the upper wall and a lower heater element array supported below the lower wall. A pyrometer is supported above the upper heater element array, is optically coupled to the interior of the chamber body, and is operably connected to the upper heater element array. A thermocouple is arranged within the interior of the chamber body, is in intimate mechanical contact with the substrate support, and is operably connected to the lower heater element array. Semiconductor processing systems and material layer deposition methods are also described.

公开(公告)号：US20250034714A1

公开(公告)日：2025-01-30

申请号：US18784060

申请日：2024-07-25

Applicant: ASM IP Holding B.V.

Inventor： Wentao Wang ,  Peipei Gao ,  Kishor Patil ,  Aniket Chitale ,  Fan Gao ,  Xing Lin ,  Alexandros Demos ,  Amir Kajbafvala ,  Emesto Suarez ,  Arun Murali ,  Caleb Miskin ,  Bubesh Babu Jotheeswaran

IPC: C23C16/46 ,  C23C16/06 ,  C23C16/458 ,  C30B25/10 ,  C30B25/12 ,  C30B29/52 ,  H01L21/02

Abstract: A reflector includes a reflector body having a slotted surface, a planar surface, and an ellipsoidal surface. The planar surface is opposite the slotted surface and is separated from the slotted surface by a thickness of the reflector body. The ellipsoidal surface is offset from the planar surface, is opposite the slotted surface and separated from the slotted surface by the thickness of the reflector body and spans the slotted surface of the reflector body. The ellipsoidal surface defines an elliptical profile that is orthogonal relative to the planar surface to concentrate heat flux at a distal focus of the elliptical profile using electromagnetic radiation reflected by the ellipsoidal surface of the reflector body. Semiconductor processing systems and material layer deposition methods are also described.

公开(公告)号：US20250079167A1

公开(公告)日：2025-03-06

申请号：US18815636

申请日：2024-08-26

Applicant: ASM IP Holding B.V.

Inventor： Ernesto Suarez ,  Amir Kajbafvala ,  Arun Murali ,  Caleb Miskin ,  Alexandros Demos

IPC: H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/167

Abstract: A method of forming a semiconductor structure includes seating a substrate on a substrate support arranged within a chamber arrangement of a semiconductor processing system, flowing a boron-containing precursor to the chamber arrangement at a first boron-containing precursor mass flow rate, and depositing a first portion of a first SiGe:B layer using the boron-containing precursor. Mass flow rate of the boron-containing precursor to an intermediate boron-containing precursor flow rate, a second portion of the first SiGe:B layer is deposited using the boron-containing precursor, mass flow rate of the boron-containing precursor to the chamber arrangement is further increased to a second boron-containing precursor mass flow rate, and a second SiGe:B layer is deposited onto the first SiGe:B layer using the boron-containing precursor, the increase in the mass flow rate of the boron-containing precursor to the intermediate boron-containing precursor mass flow rate limits boron concentration at a first SiGe:B layer-to-second SiGe:B layer interface defined between the first SiGe:B layer and the second SiGe:B layer to less than a boron concentration within the second SiGe:B layer. Semiconductor processing systems and related computer program products are also provided.

公开(公告)号：US20240175138A1

公开(公告)日：2024-05-30

申请号：US18518393

申请日：2023-11-22

Applicant: ASM IP HOlding B.V.

Inventor： Fan Gao ,  Peipei Gao ,  Xing Lin ,  Arun Murali ,  Gregory Deye ,  Frederick Aryeetey ,  Amir Kajbafvala ,  Caleb Miskin ,  Alexandros Demos

IPC: C23C16/52 ,  C23C16/44 ,  C23C16/46 ,  H01L21/67

CPC classification number: C23C16/52 ,  C23C16/4412 ,  C23C16/46 ,  H01L21/67017 ,  H01L21/67126 ,  H01L21/67253

Abstract: Systems and methods controlling the pressure differential between two sealed chambers connected by a gate valve in preparation for a gate valve opening event. Such systems and methods may adjust gas pressure in at least one of the chambers, if needed, until the pressure differential between the two chambers is at a predetermined pressure differential level. In some more specific examples, one chamber may constitute a substrate handling chamber, the other chamber may constitute a reaction chamber (e.g., for depositing one or more layers on a surface of a substrate), and the gate valve opening event may allow a substrate to be transferred from one chamber to the other (e.g., from the reaction chamber into the substrate handling chamber).