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公开(公告)号：US10474490B2
公开(公告)日：2019-11-12
申请号：US15637800
申请日：2017-06-29
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Gongxian Jeffrey Cheng , Louis Regniere , Anthony Asaro
Abstract: A technique for efficient time-division of resources in a virtualized accelerated processing device (“APD”) is provided. In a virtualization scheme implemented on the APD, different virtual machines are assigned different “time-slices” in which to use the APD. When a time-slice expires, the APD performs a virtualization context switch by stopping operations for a current virtual machine (“VM”) and starting operations for another VM. Typically, each VM is assigned a fixed length of time, after which a virtualization context switch is performed. This fixed length of time can lead to inefficiencies. Therefore, in some situations, in response to a VM having no more work to perform on the APD and the APD being idle, a virtualization context switch is performed “early.” This virtualization context switch is “early” in the sense that the virtualization context switch is performed before the fixed length of time for the time-slice expires.
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公开(公告)号：US10176548B2
公开(公告)日：2019-01-08
申请号：US14974585
申请日：2015-12-18
Applicant: ATI TECHNOLOGIES ULC
Inventor： Gongxian Jeffrey Cheng
Abstract: A processor includes a scheduler that governs which of a plurality of pending graphics contexts is selected for execution at a graphics pipeline of the processor. The processor also includes a plurality of flip queues storing data ready to be rendered at a display device. The executing graphics context can issue a flip request to change data at stored at one of the flip queues. In response to determining that the flip request targets a flip queue that is being used for rendering at the display device, the scheduler executes a context switch to schedule a different graphics context for execution at the graphics pipeline.
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公开(公告)号：US20160378674A1
公开(公告)日：2016-12-29
申请号：US14747944
申请日：2015-06-23
Applicant: ATI Technologies ULC , Advanced Micro Devices, Inc.
Inventor： Gongxian Jeffrey Cheng , Mark Fowler , Philip J. Rogers , Benjamin T. Sander , Anthony Asaro , Mike Mantor , Raja Koduri
IPC: G06F12/10
CPC classification number: G06F12/1009 , G06F12/1072 , G06F12/1081 , G06F15/163 , G06F2212/1016 , G06F2212/151 , G06F2212/152 , G06F2212/251
Abstract: A processor uses the same virtual address space for heterogeneous processing units of the processor. The processor employs different sets of page tables for different types of processing units, such as a CPU and a GPU, wherein a memory management unit uses each set of page tables to translate virtual addresses of the virtual address space to corresponding physical addresses of memory modules associated with the processor. As data is migrated between memory modules, the physical addresses in the page tables can be updated to reflect the physical location of the data for each processing unit.
Abstract translation: 处理器对处理器的异构处理单元使用相同的虚拟地址空间。 处理器对不同类型的处理单元（例如CPU和GPU）采用不同的页表，其中存储器管理单元使用每组页表来将虚拟地址空间的虚拟地址转换为存储器模块的相应物理地址 与处理器相关联。 随着数据在内存模块之间迁移，可以更新页表中的物理地址，以反映每个处理单元的数据的物理位置。
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公开(公告)号：US11100004B2
公开(公告)日：2021-08-24
申请号：US14747944
申请日：2015-06-23
Applicant: ATI Technologies ULC , Advanced Micro Devices, Inc.
Inventor： Gongxian Jeffrey Cheng , Mark Fowler , Philip J. Rogers , Benjamin T. Sander , Anthony Asaro , Mike Mantor , Raja Koduri
IPC: G06F12/1009
Abstract: A processor uses the same virtual address space for heterogeneous processing units of the processor. The processor employs different sets of page tables for different types of processing units, such as a CPU and a GPU, wherein a memory management unit uses each set of page tables to translate virtual addresses of the virtual address space to corresponding physical addresses of memory modules associated with the processor. As data is migrated between memory modules, the physical addresses in the page tables can be updated to reflect the physical location of the data for each processing unit.
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公开(公告)号：US20190004839A1
公开(公告)日：2019-01-03
申请号：US15637800
申请日：2017-06-29
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Gongxian Jeffrey Cheng , Louis Regniere , Anthony Asaro
CPC classification number: G06F9/45558 , G06F9/45533 , G06F9/461 , G06F9/4881 , G06F9/50 , G06F9/5077 , G06F2009/45575 , G06F2209/509
Abstract: A technique for efficient time-division of resources in a virtualized accelerated processing device (“APD”) is provided. In a virtualization scheme implemented on the APD, different virtual machines are assigned different “time-slices” in which to use the APD. When a time-slice expires, the APD performs a virtualization context switch by stopping operations for a current virtual machine (“VM”) and starting operations for another VM. Typically, each VM is assigned a fixed length of time, after which a virtualization context switch is performed. This fixed length of time can lead to inefficiencies. Therefore, in some situations, in response to a VM having no more work to perform on the APD and the APD being idle, a virtualization context switch is performed “early.” This virtualization context switch is “early” in the sense that the virtualization context switch is performed before the fixed length of time for the time-slice expires.
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Patent Agency Ranking
公开(公告)号：US20220269620A1
公开(公告)日：2022-08-25
申请号：US17666974
申请日：2022-02-08
Applicant: ADVANCED MICRO DEVICES, INC. , ATI Technologies ULC
Inventor： Benjamin T. SANDER , Mark Fowler , Anthony Asaro , Gongxian Jeffrey Cheng , Michael Mantor
IPC: G06F12/1027 , G06F12/0893
Abstract: A processor maintains an access log indicating a stream of cache misses at a cache of the processor. In response to each of at least a subset of cache misses at the cache, the processor records a corresponding entry in the access log, indicating a physical memory address of the memory access request that resulted in the corresponding miss. In addition, the processor maintains an address translation log that indicates a mapping of physical memory addresses to virtual memory addresses. In response to an address translation (e.g., a page walk) that translates a virtual address to a physical address, the processor stores a mapping of the physical address to the corresponding virtual address at an entry of the address translation log. Software executing at the processor can use the two logs for memory management.
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公开(公告)号：US10521389B2
公开(公告)日：2019-12-31
申请号：US15389811
申请日：2016-12-23
Applicant: ATI Technologies ULC
Inventor： Gongxian Jeffrey Cheng
IPC: G06F13/40 , G06F12/0802 , G06F13/16 , G06F13/42 , G06F12/0804 , G06F12/0868
Abstract: Described herein is a method and system for accessing a block addressable input/output (I/O) device, such as a non-volatile memory (NVM), as byte addressable memory. A front end processor connected to a Peripheral Component Interconnect Express (PCIe) switch performs as a front end interface to the block addressable I/O device to emulate byte addressability. A PCIe device, such as a graphics processing unit (GPU), can directly access the necessary bytes via the front end processor from the block addressable I/O device. The PCIe compatible devices can access data from the block I/O devices without having to go through system memory and a host processor. In an implementation, a system can include block addressable I/O, byte addressable I/O and hybrids thereof which support direct access to byte addressable memory by the host processor, GPU and any other PCIe compatible device.
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公开(公告)号：US10423354B2
公开(公告)日：2019-09-24
申请号：US14863026
申请日：2015-09-23
Applicant: Advanced Micro Devices, Inc. , ATI TECHNOLOGIES ULC
Inventor： Philip Rogers , Benjamin T. Sander , Anthony Asaro , Gongxian Jeffrey Cheng
IPC: G06F3/06 , G06F13/28 , G06F12/1009
Abstract: A memory manager of a processor identifies a block of data for eviction from a first memory module to a second memory module. In response, the processor copies only those portions of the data block that have been identified as modified portions to the second memory module. The amount of data to be copied is thereby reduced, improving memory management efficiency and reducing processor power consumption.
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公开(公告)号：US10545800B2
公开(公告)日：2020-01-28
申请号：US15610047
申请日：2017-05-31
Applicant: ATI Technologies ULC
Inventor： Anthony Asaro , Gongxian Jeffrey Cheng
Abstract: A technique for facilitating direct doorbell rings in a virtualized system is provided. A first device is configured to “ring” a “doorbell” of a second device, where both the first and second devices are not a host processor such as a central processing unit and are coupled to an interconnect fabric such as peripheral component interconnect express (“PCIe”). The first device is configured to ring the doorbell of the second device by writing to a doorbell address in a guest physical address space. For security reasons, a check block checks an offset portion of the doorbell address against a set of allowed doorbell addresses for doorbells specified in the guest physical address space, allowing the doorbell to be written if the doorbell is included in the set of allowed doorbell addresses.
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公开(公告)号：US20170178273A1
公开(公告)日：2017-06-22
申请号：US14974585
申请日：2015-12-18
Applicant: ATI TECHNOLOGIES ULC
Inventor： Gongxian Jeffrey Cheng
Abstract: A processor includes a scheduler that governs which of a plurality of pending graphics contexts is selected for execution at a graphics pipeline of the processor. The processor also includes a plurality of flip queues storing data ready to be rendered at a display device. The executing graphics context can issue a flip request to change data at stored at one of the flip queues. In response to determining that the flip request targets a flip queue that is being used for rendering at the display device, the scheduler executes a context switch to schedule a different graphics context for execution at the graphics pipeline.
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