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公开(公告)号：US11843529B2
公开(公告)日：2023-12-12
申请号：US17344330
申请日：2021-06-10
Applicant: ATI TECHNOLOGIES ULC
Inventor： Eric D. Meyer , Nima Osqueizadeh
IPC: H04W4/00 , H04L43/06 , H04L69/18 , H04L1/1607 , H04L1/1829 , H04L69/22 , H04L12/40
CPC classification number: H04L43/06 , H04L1/1607 , H04L1/1835 , H04L69/18 , H04L69/22 , H04L12/40
Abstract: A reporting device communicates with a master device by a first component and a daisy-chained second component. The reporting device receives a signal from the master device via the first component. The signal triggers the reporting device to transmit synchronously a telemetry data packet on the daisy-chained second component when a downstream device is coupled to the second component. The reporting device receives a first header packet having an address of the reporting device, transmits the telemetry data packet to the downstream device, and transmits a second header packet having an address of the downstream device.
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公开(公告)号：US10761736B2
公开(公告)日：2020-09-01
申请号：US16055716
申请日：2018-08-06
Applicant: ATI Technologies ULC , ADVANCED MICRO DEVICES, INC.
Inventor： Nima Osqueizadeh , Paul Blinzer
IPC: G06F3/06
Abstract: Described herein is a method and system for directly accessing and transferring data between a first memory architecture and a second memory architecture associated with a graphics processing unit (GPU) by treating the first memory architecture, the second memory architecture and system memory as a single physical memory, where the first memory architecture is a non-volatile memory (NVM) and the second memory architecture is a local memory. Upon accessing a virtual address (VA) range by a processor, the requested content is paged in from the single physical memory and is then redirected by a virtual storage driver to the second memory architecture or the system memory, depending on which of the GPU or CPU triggered the access request. The memory transfer occurs without awareness of the application and the operating system.
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公开(公告)号：US11063850B2
公开(公告)日：2021-07-13
申请号：US16116576
申请日：2018-08-29
Applicant: ATI TECHNOLOGIES ULC
Inventor： Eric D. Meyer , Nima Osqueizadeh
Abstract: A reporting device communicates with a master device by a first component and a daisy-chained second component. The reporting device receives a signal from the master device via the first component. The signal triggers the reporting device to transmit synchronously a telemetry data packet on the daisy-chained second component when a downstream device is coupled to the second component. The reporting device receives a first header packet having an address of the reporting device, transmits the telemetry data packet to the downstream device, and transmits a second header packet having an address of the downstream device.
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公开(公告)号：US20190243791A1
公开(公告)日：2019-08-08
申请号：US16380005
申请日：2019-04-10
Applicant: ATI Technologies ULC
Inventor： Nima Osqueizadeh
CPC classification number: G06F13/4022 , G06F13/16 , G06F13/4068
Abstract: Described herein are a method and device for transferring data in a computer system. The device includes a host processor, a plurality of first memory architectures, a switch, a redundant array of independent drives (RAID) assist unit; and a second memory architecture. The host processor is configured to send a data transfer command to the RAID assist unit via the switch. The RAID assist unit is configured to create a set of parallel memory transactions between the plurality of first memory architectures and the second memory architecture, execute the set of parallel memory transactions via the local switch and absent interaction with the host processor; and notify the host processor upon completion of data transfer. In an implementation, the plurality of first memory architectures is non-volatile memories (NVMs) and the second memory architecture is local memory.
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公开(公告)号：US20180181518A1
公开(公告)日：2018-06-28
申请号：US15389747
申请日：2016-12-23
Applicant: ATI Technologies ULC
Inventor： Nima Osqueizadeh
CPC classification number: G06F13/4022 , G06F13/16 , G06F13/4068
Abstract: Described herein are apparatus for connecting a first memory architecture locally to a graphics processing unit (GPU) through a local switch, where the first memory architecture can be a non-volatile memory (NVM) or other similarly used memories, for example, along with associated controllers. The apparatus includes the GPU(s) or discrete GPU(s) (dGPU(s)) (collectively GPU(s)), second memory architectures associated with the GPU(s), the local switch, first memory architecture(s), first memory architecture controllers or first memory architecture connector(s). In an implementation, the local switch is part of the GPU. The apparatus can also include a controller for distributing a large transaction among multiple first memory architectures. In an implementation, the first memory architectures can be directly connected to the GPU. In an implementation, the apparatus is user configurable. In an implementation, the apparatus is a solid state graphics (SSG) card.
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Patent Agency Ranking
公开(公告)号：US10678733B2
公开(公告)日：2020-06-09
申请号：US16380005
申请日：2019-04-10
Applicant: ATI Technologies ULC
Inventor： Nima Osqueizadeh
Abstract: Described herein are a method and device for transferring data in a computer system. The device includes a host processor, a plurality of first memory architectures, a switch, a redundant array of independent drives (RAID) assist unit; and a second memory architecture. The host processor is configured to send a data transfer command to the RAID assist unit via the switch. The RAID assist unit is configured to create a set of parallel memory transactions between the plurality of first memory architectures and the second memory architecture, execute the set of parallel memory transactions via the local switch and absent interaction with the host processor; and notify the host processor upon completion of data transfer. In an implementation, the plurality of first memory architectures is non-volatile memories (NVMs) and the second memory architecture is local memory.
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公开(公告)号：US10445275B2
公开(公告)日：2019-10-15
申请号：US15582479
申请日：2017-04-28
Applicant: ATI Technologies ULC
Inventor： Nima Osqueizadeh
Abstract: Described is a solid state graphics (SSG) subsystem including a die and a package, where the die includes a memory hub, graphics processing unit(s) (GPU(s)) connected to the memory hub, first memory architecture controller(s) connected to the memory hub and directly controlling access to first memory architecture(s), second memory architecture controller associated with each GPU and each second memory architecture controller connected to the memory hub and second memory architecture(s), an expansion bus first memory architecture controller connected to the memory hub and being an endpoint for a host system and an expansion bus controller coupled to the expansion bus first memory architecture controller and capable of connecting to the host system. The first memory architecture(s) and the second memory architecture(s) are either located on the SSG subsystem, located on the package, or a combination thereof.
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公开(公告)号：US10268620B2
公开(公告)日：2019-04-23
申请号：US15389747
申请日：2016-12-23
Applicant: ATI Technologies ULC
Inventor： Nima Osqueizadeh
Abstract: Described herein are apparatus for connecting a first memory architecture locally to a graphics processing unit (GPU) through a local switch, where the first memory architecture can be a non-volatile memory (NVM) or other similarly used memories, for example, along with associated controllers. The apparatus includes the GPU(s) or discrete GPU(s) (dGPU(s)) (collectively GPU(s)), second memory architectures associated with the GPU(s), the local switch, first memory architecture(s), first memory architecture controllers or first memory architecture connector(s). In an implementation, the local switch is part of the GPU. The apparatus can also include a controller for distributing a large transaction among multiple first memory architectures. In an implementation, the first memory architectures can be directly connected to the GPU. In an implementation, the apparatus is user configurable. In an implementation, the apparatus is a solid state graphics (SSG) card.
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公开(公告)号：US20180181520A1
公开(公告)日：2018-06-28
申请号：US15582479
申请日：2017-04-28
Applicant: ATI Technologies ULC
Inventor： Nima Osqueizadeh
CPC classification number: G06F13/4022 , G06F13/1668 , G06F13/4068 , G06F13/4282
Abstract: Described is a solid state graphics (SSG) subsystem including a die and a package, where the die includes a memory hub, graphics processing unit(s) (GPU(s)) connected to the memory hub, first memory architecture controller(s) connected to the memory hub and directly controlling access to first memory architecture(s), second memory architecture controller associated with each GPU and each second memory architecture controller connected to the memory hub and second memory architecture(s), an expansion bus first memory architecture controller connected to the memory hub and being an endpoint for a host system and an expansion bus controller coupled to the expansion bus first memory architecture controller and capable of connecting to the host system. The first memory architecture(s) and the second memory architecture(s) are either located on the SSG subsystem, located on the package, or a combination thereof.
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公开(公告)号：US20180181340A1
公开(公告)日：2018-06-28
申请号：US15389596
申请日：2016-12-23
Applicant: ATI Technologies ULC
Inventor： Nima Osqueizadeh
IPC: G06F3/06
CPC classification number: G06F3/0611 , G06F3/0635 , G06F3/0658 , G06F3/068 , G06F3/0685
Abstract: Described herein is a method and system for directly accessing and transferring data between a first memory architecture and a second memory architecture associated with a graphics processing unit (GPU) or a discrete GPU (dGPU). In particular, a method is described for transferring data between the first memory architecture and the second memory architecture that bypasses interaction with a system memory of a processor and a root complex. A transfer command is sent from the processor, (or a host agent in the GPU or dGPU), to a first memory architecture controller. The first memory architecture controller initiates the transfer of the data directly between the first memory architecture and the second memory architecture. The method bypasses: 1) a host root complex; and 2) storing the data in the system memory and then having to transfer the data to the second memory architecture or the first memory architecture.
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