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18 条记录 (耗时 0.027 秒)

    Latency normalization by balancing early and late clocks
    4.
    发明授权
    Latency normalization by balancing early and late clocks 有权
    通过平衡早期和晚期时钟的延迟归一化

    公开(公告)号：US07324403B2

    公开(公告)日：2008-01-29

    申请号：US10949053

    申请日：2004-09-24

    申请人： Hing Yan To ,  Joe Salmon ,  Mamun Ur Rashid

    发明人： Hing Yan To ,  Joe Salmon ,  Mamun Ur Rashid

    IPC分类号： G11C8/18

    CPC分类号： G06F1/10

    摘要： A method, apparatus, and system are disclosed. In one embodiment the method comprises inputting an early clock signal and a late clock signal to a memory device and generating an average clock signal for the memory device by averaging the early clock signal and the late clock signal.

    摘要翻译： 公开了一种方法，装置和系统。 在一个实施例中，该方法包括将早期时钟信号和后期时钟信号输入到存储器件，并通过对早期时钟信号和后期时钟信号进行平均来产生存储器件的平均时钟信号。

    Clocking architecture using a bidirectional clock port
    5.
    发明授权
    Clocking architecture using a bidirectional clock port 有权
    使用双向时钟端口的时钟架构

    公开(公告)号：US07555670B2

    公开(公告)日：2009-06-30

    申请号：US11260019

    申请日：2005-10-26

    申请人： Ravindran Mohanavelu ,  Aaron K. Martin ,  Dawson Kesling ,  Joe Salmon ,  Mamun Ur Rashid

    发明人： Ravindran Mohanavelu ,  Aaron K. Martin ,  Dawson Kesling ,  Joe Salmon ,  Mamun Ur Rashid

    IPC分类号： G06F1/04 ,  G11C8/00

    CPC分类号： G06F1/04 ,  G06F1/10

    摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for a clocking architecture using a bidirectional clock. In an embodiment, a chip includes a bidirectional clock port capable of being statically configured to receive or to transmit a reference clock. In one embodiment, the chip includes a first port to receive data and a second port, wherein the chip repeats at least a portion of the data that it receives on the first port to a transmitter at the second port. Other embodiments are described and claimed.

    摘要翻译： 本发明的实施例一般涉及使用双向时钟的时钟架构的系统，方法和装置。 在一个实施例中，芯片包括能够静态配置为接收或传输参考时钟的双向时钟端口。 在一个实施例中，芯片包括用于接收数据的第一端口和第二端口，其中芯片将其在第一端口上接收的数据的至少一部分重复到第二端口处的发送器。 描述和要求保护其他实施例。

    Receive clock deskewing method, apparatus, and system
    6.
    发明授权
    Receive clock deskewing method, apparatus, and system 有权
    接收时钟去歪斜方法，仪器和系统

    公开(公告)号：US07439788B2

    公开(公告)日：2008-10-21

    申请号：US11319689

    申请日：2005-12-28

    申请人： Hon-Mo Raymond Law ,  Mamun Ur Rashid ,  Aaron K. Martin

    发明人： Hon-Mo Raymond Law ,  Mamun Ur Rashid ,  Aaron K. Martin

    IPC分类号： H03K5/13

    CPC分类号： H04L7/033 ,  H03L7/07 ,  H03L7/0814 ,  H04L7/0337

    摘要： An integrated circuit includes clock deskew circuitry. The deskew circuitry includes multiple loop circuits to align a received clock with a data eye, and to reduce the effects of clock drift caused by voltage and temperature variations. The loop circuits include phase interpolators to produce local clock signals. Local clock signals are provided to seqiuential elements through local clock trees and are also provided to a phase detector through a dummy local clock tree. The operation of the phase interpolators is influenced by the phase detector.

    摘要翻译： 集成电路包括时钟偏移电路。 该偏斜电路包括多个回路电路，以使接收的时钟与数据眼对齐，并且减少由电压和温度变化引起的时钟漂移的影响。 环路电路包括产生本地时钟信号的相位插值器。 本地时钟信号通过本地时钟树提供给连续元件，并且还通过虚拟本地时钟树提供给相位检测器。 相位内插器的操作受相位检测器的影响。

    Even and odd frame combination data path architecture
    7.
    发明授权
    Even and odd frame combination data path architecture 有权
    偶数和奇数帧组合数据路径架构

    公开(公告)号：US08225016B2

    公开(公告)日：2012-07-17

    申请号：US12006247

    申请日：2007-12-31

    申请人： Mamun Ur Rashid

    发明人： Mamun Ur Rashid

    IPC分类号： G06F13/12

    CPC分类号： G06F13/4059 ,  Y02D10/14 ,  Y02D10/151

    摘要： Methods and apparatus to odd and even frame combination data path architectures are described. In one embodiment, a logic may include a buffer and a parallel input, serial output (PISO) logic that may be utilized for transferring data between a source and a destination. The logic may be utilized for transferring the data whether or not the data is transmitted in accordance with single ended or differential signals. Other embodiments are also described.

    摘要翻译： 描述了奇数和偶数帧组合数据路径架构的方法和装置。 在一个实施例中，逻辑可以包括可用于在源和目的地之间传送数据的缓冲器和并行输入串行输出（PISO）逻辑。 逻辑可以用于传送数据，无论数据是根据单端还是差分信号发送的。 还描述了其它实施例。

    Even and odd frame combination data path architecture
    8.
    发明申请
    Even and odd frame combination data path architecture 有权
    偶数和奇数帧组合数据路径架构

    公开(公告)号：US20090172215A1

    公开(公告)日：2009-07-02

    申请号：US12006247

    申请日：2007-12-31

    申请人： Mamun Ur Rashid

    发明人： Mamun Ur Rashid

    IPC分类号： G06F13/00

    CPC分类号： G06F13/4059 ,  Y02D10/14 ,  Y02D10/151

    摘要： Methods and apparatus to odd and even frame combination data path architectures are described. In one embodiment, a logic may include a buffer and a parallel input, serial output (PISO) logic that may be utilized for transferring data between a source and a destination. The logic may be utilized for transferring the data whether or not the data is transmitted in accordance with single ended or differential signals. Other embodiments are also described.

    摘要翻译： 描述了奇数和偶数帧组合数据路径架构的方法和装置。 在一个实施例中，逻辑可以包括可用于在源和目的地之间传送数据的缓冲器和并行输入串行输出（PISO）逻辑。 逻辑可以用于传送数据，无论数据是根据单端还是差分信号发送的。 还描述了其它实施例。

    MODULAR MEMORY CONTROLLER CLOCKING ARCHITECTURE
    10.
    发明申请
    MODULAR MEMORY CONTROLLER CLOCKING ARCHITECTURE 有权
    模块化记忆控制器时钟结构

    公开(公告)号：US20080162977A1

    公开(公告)日：2008-07-03

    申请号：US11647656

    申请日：2006-12-28

    申请人： Hing To ,  Mamun Ur Rashid

    发明人： Hing To ,  Mamun Ur Rashid

    IPC分类号： G06F1/04

    CPC分类号： H03L7/0812 ,  H03L7/0805

    摘要： According to one embodiment, a memory controller is disclosed. The memory controller includes a phase locked loop (PLL) to generate a differential reference clock and a first clocking component coupled to the PLL. The first clocking component includes a first delay locked loop (DLL) to receive the reference clock and to generate transmit and receive delay de-skew clock signals, a first set of phase interpolators to provide data transmit de-skewing and a first set of slave delay lines to provide data receive de-skewing.

    摘要翻译： 根据一个实施例，公开了一种存储器控制器。 存储器控制器包括产生差分参考时钟的锁相环（PLL）和耦合到PLL的第一时钟元件。 第一时钟元件包括接收参考时钟并产生发射和接收延迟去偏移时钟信号的第一延迟锁定环路（DLL），提供数据发射去偏移的第一组相位内插器和第一组从站 延迟线提供数据接收去偏移。