公开(公告)号：US07808827B2

公开(公告)日：2010-10-05

申请号：US11935717

申请日：2007-11-06

申请人： Aaron Lee ,  Nian Yang ,  Jiani Zhang

发明人： Aaron Lee ,  Nian Yang ,  Jiani Zhang

IPC分类号： G11C11/34

CPC分类号： G11C16/0416 ,  G11C11/5635 ,  G11C16/16 ,  G11C16/24 ,  G11C16/3418 ,  G11C16/3427

摘要： Systems and/or methods that facilitate discharging bit lines (BL) associated with memory arrays in nonvolatile memory at a controlled rate are presented. A discharge component facilitates discharging the BL at a desired rate thus preventing the “hot switching” phenomenon from occurring within a y-decoder component(s) associated with the nonvolatile memory. The discharge component can be comprised of, in part, a discharge transistor component that controls the rate of BL discharge wherein the gate voltage of the discharge transistor component can be controlled by a discharge controller component. The rate of BL discharge can be determined by the size of discharge transistor component used in the design, the strength and/or size of the y-decoder component, the number of erase errors that occur for a particular memory device, and/or other factors in order to facilitate preventing hot switching from occurring.

摘要翻译： 提出了有助于以受控的速率放电与非易失性存储器中的存储器阵列相关联的位线（BL）的系统和/或方法。 放电元件有助于以期望的速率放电BL，从而防止在与非易失性存储器相关联的y解码器组件内发生“热切换”现象。 放电部件可以部分地由控制BL放电速率的放电晶体管部件组成，其中放电晶体管部件的栅极电压可以由放电控制器部件控制。 BL放电的速率可以由设计中使用的放电晶体管组件的大小，y解码器组件的强度和/或尺寸，特定存储器件发生的擦除错误的数量和/或其他 因素，以便于防止发生热切换。

公开(公告)号：US20090119447A1

公开(公告)日：2009-05-07

申请号：US11935717

申请日：2007-11-06

申请人： Aaron Lee ,  Nian Yang ,  Jiani Zhang

发明人： Aaron Lee ,  Nian Yang ,  Jiani Zhang

IPC分类号： G06F12/00

CPC分类号： G11C16/0416 ,  G11C11/5635 ,  G11C16/16 ,  G11C16/24 ,  G11C16/3418 ,  G11C16/3427

摘要： Systems and/or methods that facilitate discharging bit lines (BL) associated with memory arrays in nonvolatile memory at a controlled rate are presented. A discharge component facilitates discharging the BL at a desired rate thus preventing the “hot switching” phenomenon from occurring within a y-decoder component(s) associated with the nonvolatile memory. The discharge component can be comprised of, in part, a discharge transistor component that controls the rate of BL discharge wherein the gate voltage of the discharge transistor component can be controlled by a discharge controller component. The rate of BL discharge can be determined by the size of discharge transistor component used in the design, the strength and/or size of the y-decoder component, the number of erase errors that occur for a particular memory device, and/or other factors in order to facilitate preventing hot switching from occurring.

摘要翻译： 提出了有助于以受控的速率放电与非易失性存储器中的存储器阵列相关联的位线（BL）的系统和/或方法。 放电元件有助于以期望的速率放电BL，从而防止在与非易失性存储器相关联的y解码器组件内发生“热切换”现象。 放电部件可以部分地由控制BL放电速率的放电晶体管部件组成，其中放电晶体管部件的栅极电压可以由放电控制器部件控制。 BL放电的速率可以由设计中使用的放电晶体管组件的大小，y解码器组件的强度和/或尺寸，特定存储器件发生的擦除错误的数量和/或其他 因素，以便于防止发生热切换。

公开(公告)号：US07613042B2

公开(公告)日：2009-11-03

申请号：US11935049

申请日：2007-11-05

申请人： Jiani Zhang ,  Nian Yang ,  Aaron Lee

发明人： Jiani Zhang ,  Nian Yang ,  Aaron Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/0475 ,  G11C11/5671 ,  G11C16/14 ,  H01L29/7881 ,  H01L29/7923

摘要： Methods and apparatus are disclosed for erasing memory cells in a virtual ground memory core, wherein a row decoder apparatus employs a protective voltage to wordlines of a sector of cells while concurrently providing an erase voltage to selected wordlines of the same physical sector. Decoder circuitry and methods are disclosed for selecting a memory cell sector to be erased and adjacent sectors to be protected, which may be used in single bit and dual bit memory devices, and which enable column decoder circuitry to reduce the number of sector select circuits.

摘要翻译： 公开了用于擦除虚拟地址存储器核心中的存储器单元的方法和装置，其中行解码器装置对单元扇区的字线采用保护电压，同时向同一物理扇区的选定字线提供擦除电压。 公开了用于选择要擦除的存储器单元扇区和要被保护的相邻扇区的解码器电路和方法，其可以在单比特和双比特存储器件中使用，并且使得列解码器电路能够减少扇区选择电路的数量。

公开(公告)号：US20090116289A1

公开(公告)日：2009-05-07

申请号：US11935049

申请日：2007-11-05

申请人： Jiani Zhang ,  Nian Yang ,  Aaron Lee

发明人： Jiani Zhang ,  Nian Yang ,  Aaron Lee

IPC分类号： G11C16/08 ,  H01L21/8229

CPC分类号： G11C16/0475 ,  G11C11/5671 ,  G11C16/14 ,  H01L29/7881 ,  H01L29/7923

摘要： Methods and apparatus are disclosed for erasing memory cells in a virtual ground memory core, wherein a row decoder apparatus employs a protective voltage to wordlines of a sector of cells while concurrently providing an erase voltage to selected wordlines of the same physical sector. Decoder circuitry and methods arc disclosed for selecting a memory cell sector to be erased and adjacent sectors to be protected, which may be used in single bit and dual bit memory devices, and which enable column decoder circuitry to reduce the number of sector select circuits.

摘要翻译： 公开了用于擦除虚拟地址存储器核心中的存储器单元的方法和装置，其中行解码器装置对单元扇区的字线采用保护电压，同时向同一物理扇区的选定字线提供擦除电压。 公开了用于选择要擦除的存储器单元扇区和要被保护的相邻扇区的解码器电路和方法，其可以在单比特和双比特存储器件中使用，并且使得列解码器电路能够减少扇区选择电路的数量。

公开(公告)号：US07196938B1

公开(公告)日：2007-03-27

申请号：US11229530

申请日：2005-09-20

申请人： Yonggang Wu ,  Guowei Wang ,  Nian Yang ,  Aaron Lee

发明人： Yonggang Wu ,  Guowei Wang ,  Nian Yang ,  Aaron Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/12

摘要： A non-volatile memory cell array, such as a Flash NOR array, is programmed by applying voltages to bit lines that connect to memory cells in the memory cell array. A first bit line corresponding to a first memory cell in the memory array may be turned on to perform a first programming operation for the first memory cell and second bit line corresponding to a second memory cell in the memory array may be turned on to perform a second programming operation that is configured to complete after the first programming operation. The turning on/off of the first and second bit lines may be overlapped to share charge between the first and second bit lines. This overlapping can reduce wasted power and decrease programming pulse overshoot problems.

摘要翻译： 诸如闪存NOR阵列的非易失性存储单元阵列通过将电压施加到连接到存储单元阵列中的存储单元的位线来编程。 对应于存储器阵列中的第一存储器单元的第一位线可以被接通以对第一存储器单元执行第一编程操作，并且可以打开与存储器阵列中的第二存储器单元相对应的第二位线来执行 第二编程操作被配置为在第一编程操作之后完成。 第一和第二位线的导通/截止可以重叠以在第一和第二位线之间共享电荷。 这种重叠可以减少浪费的功率并减少编程脉冲过冲问题。

公开(公告)号：US20070064464A1

公开(公告)日：2007-03-22

申请号：US11229527

申请日：2005-09-20

申请人： Tiao-Hua Kuo ,  Nancy Leong ,  Nian Yang ,  Guowei Wang ,  Aaron Lee ,  Sachit Chandra ,  Michael VanBuskirk ,  Johnny Chen ,  Darlene Hamilton ,  Binh Le

发明人： Tiao-Hua Kuo ,  Nancy Leong ,  Nian Yang ,  Guowei Wang ,  Aaron Lee ,  Sachit Chandra ,  Michael VanBuskirk ,  Johnny Chen ,  Darlene Hamilton ,  Binh Le

IPC分类号： G11C17/00

CPC分类号： G11C5/147 ,  G11C16/12

摘要： A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window containing a predetermined number of bits that are to be programmed in the array and determining which of the predetermined number of bits are to be programmed in the memory array. The predetermined number of bits are simultaneously programmed to corresponding memory cells in the array. A programming state of the predetermined number of bits in the array is simultaneously verified.

摘要翻译： 提供了一种用于对包括存储器单元阵列的非易失性存储器阵列进行编程的方法，其中每个存储单元包括衬底，控制栅极，电荷存储元件，源极区域和漏极区域。 该方法包括接收包含要在阵列中被编程的预定数量的位的编程窗口，并且确定在存储器阵列中哪个预定位数被编程。 预定数量的位同时被编程到阵列中的对应存储器单元。 同时验证阵列中预定位数的编程状态。

公开(公告)号：US07443732B2

公开(公告)日：2008-10-28

申请号：US11229527

申请日：2005-09-20

申请人： Tiao-Hua Kuo ,  Nancy Leong ,  Nian Yang ,  Guowei Wang ,  Aaron Lee ,  Sachit Chandra ,  Michael A. VanBuskirk ,  Johnny Chen ,  Darlene Hamilton ,  Binh Quang Le

发明人： Tiao-Hua Kuo ,  Nancy Leong ,  Nian Yang ,  Guowei Wang ,  Aaron Lee ,  Sachit Chandra ,  Michael A. VanBuskirk ,  Johnny Chen ,  Darlene Hamilton ,  Binh Quang Le

IPC分类号： G11C11/34

CPC分类号： G11C5/147 ,  G11C16/12

摘要： A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window containing a predetermined number of bits that are to be programmed in the array and determining which of the predetermined number of bits are to be programmed in the memory array. The predetermined number of bits are simultaneously programmed to corresponding memory cells in the array. A programming state of the predetermined number of bits in the array is simultaneously verified.

摘要翻译： 提供了一种用于对包括存储器单元阵列的非易失性存储器阵列进行编程的方法，其中每个存储单元包括衬底，控制栅极，电荷存储元件，源极区域和漏极区域。 该方法包括接收包含要在阵列中被编程的预定数量的位的编程窗口，并且确定在存储器阵列中哪个预定位数被编程。 预定数量的位同时被编程到阵列中的对应存储器单元。 同时验证阵列中预定位数的编程状态。

公开(公告)号：US07532518B2

公开(公告)日：2009-05-12

申请号：US11767622

申请日：2007-06-25

申请人： Nian Yang ,  Fan Wan Lai ,  Aaron Lee

发明人： Nian Yang ,  Fan Wan Lai ,  Aaron Lee

IPC分类号： G11C16/06

CPC分类号： G11C16/30 ,  G11C16/10

摘要： Systems and methodologies are provided herein for increasing operation speed uniformity in a flash memory device. Due to the characteristics of a typical flash memory array, memory cells in a memory array may experience distributed substrate resistance that increases as the distance of the memory cell from an edge of the memory array increases. This difference in distributed substrate resistance can vary voltages supplied to different memory cells in the memory array depending on their location, which can in turn cause non-uniformity in the speed of high voltage operations on the memory array such as programming. The systems and methodologies provided herein reduce this non-uniformity in operation speed by providing compensated voltage levels to memory cells in a memory array based at least in part on the location of each respective memory cell. For example, a compensated operation voltage can be provided that is higher near the center of the memory array and lower near an edge of the memory array, thereby lessening the effect of distributed substrate resistance and providing increased operation speed uniformity throughout the memory array.

摘要翻译： 本文提供的系统和方法用于提高闪存设备中的操作速度均匀性。 由于典型的闪存阵列的特征，存储器阵列中的存储器单元可能经历分布式衬底电阻，随着存储器单元与存储器阵列的边缘的距离增加而增加。 分布式基板电阻的这种差异可以根据其位置改变提供给存储器阵列中的不同存储单元的电压，这进而导致存储器阵列上的高电压操作的速度（例如编程）的不一致。 本文提供的系统和方法通过至少部分地基于每个相应存储器单元的位置，通过向存储器阵列中的存储器单元提供补偿的电压电平来降低操作速度的不均匀性。 例如，可以提供补偿操作电压，其在存储器阵列的中心附近较高，并且在存储器阵列的边缘附近较低，从而减小分布式衬底电阻的影响并且提供整个存储器阵列中的增加的操作速度均匀性。

公开(公告)号：US20080316830A1

公开(公告)日：2008-12-25

申请号：US11767622

申请日：2007-06-25

申请人： Nian Yang ,  Fan Wan Lai ,  Aaron Lee

发明人： Nian Yang ,  Fan Wan Lai ,  Aaron Lee

IPC分类号： G11C7/00

CPC分类号： G11C16/30 ,  G11C16/10

摘要： Systems and methodologies are provided herein for increasing operation speed uniformity in a flash memory device. Due to the characteristics of a typical flash memory array, memory cells in a memory array may experience distributed substrate resistance that increases as the distance of the memory cell from an edge of the memory array increases. This difference in distributed substrate resistance can vary voltages supplied to different memory cells in the memory array depending on their location, which can in turn cause non-uniformity in the speed of high voltage operations on the memory array such as programming. The systems and methodologies provided herein reduce this non-uniformity in operation speed by providing compensated voltage levels to memory cells in a memory array based at least in part on the location of each respective memory cell. For example, a compensated operation voltage can be provided that is higher near the center of the memory array and lower near an edge of the memory array, thereby lessening the effect of distributed substrate resistance and providing increased operation speed uniformity throughout the memory array.

摘要翻译： 本文提供的系统和方法用于提高闪存设备中的操作速度均匀性。 由于典型的闪存阵列的特征，存储器阵列中的存储器单元可能经历分布式衬底电阻，随着存储器单元与存储器阵列的边缘的距离增加而增加。 分布式基板电阻的这种差异可以根据其位置改变提供给存储器阵列中的不同存储单元的电压，这进而导致存储器阵列上的高电压操作的速度（例如编程）的不一致。 本文提供的系统和方法通过至少部分地基于每个相应存储器单元的位置，通过向存储器阵列中的存储器单元提供补偿的电压电平来降低操作速度的不均匀性。 例如，可以提供补偿操作电压，其在存储器阵列的中心附近较高，并且在存储器阵列的边缘附近较低，从而减小分布式衬底电阻的影响并且提供整个存储器阵列中的增加的操作速度均匀性。

公开(公告)号：US20080151639A1

公开(公告)日：2008-06-26

申请号：US11613383

申请日：2006-12-20

申请人： Nian Yang ,  Yonggang Wu ,  Aaron Lee ,  Wei Daisy Cai

发明人： Nian Yang ,  Yonggang Wu ,  Aaron Lee ,  Wei Daisy Cai

IPC分类号： G11C16/32

CPC分类号： G11C16/12

摘要： A semiconductor memory device (104) selectably connectable to an external high voltage power supply (122) is provided. The semiconductor memory device (104) includes a switch (314), a detector (316) and a timing device (318). The switch (314) is connected to external voltage supply signals and selectably couples the external voltage supply signals to memory cells (305) of the semiconductor memory device (104) for memory operations thereof. The external voltage supply signals including a high voltage signal (412) provided from the external high voltage power supply (122) and an operational voltage signal Vcc (402). The detector (316) is connected to the external voltage supply signals for generating a timer activation signal (404) in response to detecting an operational voltage power-on period. The timing device (318) signals the switch (314) to decouple the high voltage signal (412) and the operational voltage signal (402) from the memory cells (305) in response to the timer activation signal (404) and to recouple the high voltage signal (412) and the operational voltage signal (402) to the memory cells (305) a time delay interval thereafter. The time delay interval is determined in response to the high voltage signal (412).

摘要翻译： 提供可选择地连接到外部高压电源（122）的半导体存储器件（104）。 半导体存储器件（104）包括开关（314），检测器（316）和定时装置（318）。 开关（314）连接到外部电压源信号，并且可选择地将外部电压供应信号耦合到半导体存储器件（104）的存储单元（305），用于存储器操作。 包括从外部高压电源（122）提供的高电压信号（412）的外部电压供给信号和操作电压信号Vcc（402）。 检测器（316）连接到外部电压源信号，以响应于检测到工作电压通电周期而产生定时器激活信号（404）。 定时装置（318）响应于定时器启动信号（404），向开关314通知高压信号412和操作电压信号402与存储单元305的耦合， 高电压信号（412）和操作电压信号（402）到其后的时间延迟区间。 响应于高电压信号确定时间延迟间隔（412）。