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    MEMORY DEVICE AND METHOD
    3.
    发明申请
    MEMORY DEVICE AND METHOD 有权
    存储器件和方法

    公开(公告)号：US20110235430A1

    公开(公告)日：2011-09-29

    申请号：US13154616

    申请日：2011-06-07

    申请人： Bruce Lee Morton ,  Michael VanBuskirk

    发明人： Bruce Lee Morton ,  Michael VanBuskirk

    IPC分类号： G11C16/28

    CPC分类号： G11C7/12 ,  G11C7/02 ,  G11C7/062 ,  G11C7/18 ,  G11C8/12 ,  G11C16/0483 ,  G11C16/26

    摘要： During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a plurality of NAND strings and a buffer are formed.

    摘要翻译： 在第一读取周期的第一部分期间，确定读出放大器的第一输入是在读周期的第一部分期间基于存储单元的状态接收信息，并且确定第一输入处的电导基本相等 在第一部分期间到感测放大器的第二输入处的电导。 多个NAND串模块连接到存储器件的全局位线，该存储器件包括形成多个NAND串和缓冲器的存储器列。

    Memory erase management system
    4.
    发明授权
    Memory erase management system 有权
    内存擦除管理系统

    公开(公告)号：US07443712B2

    公开(公告)日：2008-10-28

    申请号：US11470958

    申请日：2006-09-07

    申请人： Colin Bill ,  Mark McClain ,  Michael VanBuskirk

    发明人： Colin Bill ,  Mark McClain ,  Michael VanBuskirk

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0097 ,  G11C2013/0076 ,  G11C2013/0078 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/79

    摘要： A memory erase management system is provided, including providing a resistive change memory cell, coupling a first line to the resistive change memory cell, coupling a line buffer to the first line, providing a charge storage device coupled to the line buffer, and performing a single pulse erase of the resistive change memory cell by discharging a current from the charge storage device through the resistive change memory cell.

    摘要翻译： 提供了一种存储器擦除管理系统，包括提供电阻变化存储单元，将第一行耦合到电阻变化存储单元，将行缓冲器耦合到第一行，提供耦合到行缓冲器的电荷存储装置，以及执行 通过从电荷存储装置通过电阻变化存储单元放电电流来对电阻变化存储单元进行单次脉冲擦除。

    Non-volatile memory string module with buffer and method
    5.
    发明授权
    Non-volatile memory string module with buffer and method 有权
    具有缓冲区和方法的非易失性存储器字符串模块

    公开(公告)号：US07830716B2

    公开(公告)日：2010-11-09

    申请号：US12134898

    申请日：2008-06-06

    申请人： Bruce Lee Morton ,  Michael VanBuskirk

    发明人： Bruce Lee Morton ,  Michael VanBuskirk

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0483 ,  G11C16/26 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11565

    摘要： During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a plurality of NAND strings and a buffer are formed.

    摘要翻译： 在第一读取周期的第一部分期间，确定读出放大器的第一输入是在读周期的第一部分期间基于存储单元的状态接收信息，并且确定第一输入处的电导基本相等 在第一部分期间到感测放大器的第二输入处的电导。 多个NAND串模块连接到存储器件的全局位线，该存储器件包括形成多个NAND串和缓冲器的存储器列。

    MULTIPOINT PROCESSING UNIT
    8.
    发明申请
    MULTIPOINT PROCESSING UNIT 有权
    多点加工单元

    公开(公告)号：US20080005246A1

    公开(公告)日：2008-01-03

    申请号：US11838798

    申请日：2007-08-14

    申请人： Michael VanBuskirk ,  Philippe Ferriere ,  Mu Han

    发明人： Michael VanBuskirk ,  Philippe Ferriere ,  Mu Han

    IPC分类号： G06F15/16 ,  G06F3/00

    CPC分类号： H04L65/4038 ,  H04L12/1822 ,  H04L65/103 ,  H04L65/104 ,  H04L65/605 ,  H04L69/08 ,  H04N7/152

    摘要： A system to provide a multipoint processing terminal and a multicast bridging terminal to provide mixing, switching, and other processing of media streams under the control of H.323 components. Application Programming Interfaces defined for the multipoint processing terminal provide a multipoint control unit with the capability to change the default behavior of the multipoint processing terminal by allowing the multipoint control unit to control the routing audio and video streams in the multipoint processing terminal and control the media formats in a multipoint conference. Multipoint processing acceleration functionality is provided by providing interfaces to allow hardware accelerated implementations of multipoint processing terminals. The multicast bridging terminals enables clients using one type of control signaling and media streaming to join other conferences using different types of control signaling and media streaming by receiving audio or video data from an incoming media stream and performing any processing necessary to transform the media stream from the incoming stream data format to the outgoing stream data format.

    摘要翻译： 一种提供多点处理终端和组播桥接终端的系统，用于在H.323组件的控制下提供媒体流的混合，切换和其他处理。 应用程序编程为多点处理终端定义的接口提供多点控制单元，具有通过允许多点控制单元控制多点处理终端中的路由音频和视频流并控制媒体的能力来改变多点处理终端的默认行为的能力 多点会议中的格式。 通过提供允许多点处理终端的硬件加速实现的接口来提供多点处理加速功能。 组播桥接终端使得客户端能够使用一种类型的控制信令和媒体流来使用不同类型的控制信令和媒体流来连接其他会议，通过从传入的媒体流接收音频或视频数据，并执行将媒体流从 输入流数据格式为输出流数据格式。

    Write-once read-many times memory
    9.
    发明申请
    Write-once read-many times memory 有权
    一次写入多次内存

    公开(公告)号：US20060221713A1

    公开(公告)日：2006-10-05

    申请号：US11095849

    申请日：2005-03-31

    申请人： Michael VanBuskirk ,  Colin Bill ,  Zhida Lan ,  Tzu-Ning Fang

    发明人： Michael VanBuskirk ,  Colin Bill ,  Zhida Lan ,  Tzu-Ning Fang

    IPC分类号： G11C7/10

    CPC分类号： G11C13/0014 ,  B82Y10/00

    摘要： A write-once read-many times memory device is made up of first and second electrodes, a passive layer between the first and second electrodes, and an active layer between the first and second electrode. The memory device is programmed by providing a charged species from the passive layer into the active layer. The memory device may be programmed to have for the programmed memory device a first erase activation energy. The present method provides for the programmed memory device a second erase activation energy greater than the first erase activation energy.

    摘要翻译： 一次写入多次存储器件由第一和第二电极，第一和第二电极之间的无源层以及第一和第二电极之间的有源层组成。 通过从被动层提供带电物质到活性层来对存储器件进行编程。 存储器件可以被编程为使编程的存储器件具有第一擦除激活能量。 本方法为编程的存储器件提供大于第一擦除激活能量的第二擦除激活能量。

    Chained array of sequential access memories enabling continuous read
    10.
    发明授权
    Chained array of sequential access memories enabling continuous read 有权
    连续读取串行存取存储器阵列

    公开(公告)号：US06622201B1

    公开(公告)日：2003-09-16

    申请号：US09525078

    申请日：2000-03-14

    申请人： Michael VanBuskirk ,  Pau-Ling Chen

    发明人： Michael VanBuskirk ,  Pau-Ling Chen

    IPC分类号： G06F1200

    CPC分类号： G11C7/22

    摘要： A sequential access memory structure includes an output bus and a plurality of sequential access memories, each of which is connected to the output bus. Each memory includes a memory array having a plurality of sequentially readable memory elements, a carry output for producing a carry signal when reading of the array has been substantially completed, and a carry input for causing reading of the array in response to a carry signal. The carry output of each memory is connected to a carry input of one other downstream memory respectively in a chain arrangement, and the carry signals cause the arrays to be read sequentially onto the output bus. Each memory further comprises a read-write storage connected between the array and the output bus, the storage including a plurality of sections. Data from the array is loaded into one section of the storage while data is being read from another section of the storage onto the output bus. The sections of memory elements in the array comprise half-pages. The storage comprises two sections, each of which has a half-page of memory elements, and the carry output produces the carry signal prior to reading data from a last half-page of the array out of the storage onto the output bus. Data from the last half-page is read onto the output bus while data from a first half-page of an array of a next downstream memory is being loaded into its storage.

    摘要翻译： 顺序访问存储器结构包括输出总线和多个顺序存取存储器，每个存取存储器连接到输出总线。 每个存储器包括具有多个可顺序读取的存储器元件的存储器阵列，当阵列的读取已基本完成时用于产生进位信号的进位输出，以及用于响应于进位信号而引起阵列读取的进位输入。 每个存储器的进位输出分别以链排列连接到另一个下游存储器的进位输入，并且进位信号使得阵列被顺序读取到输出总线上。 每个存储器还包括连接在阵列和输出总线之间的读写存储器，存储器包括多个部分。 来自阵列的数据被加载到存储的一部分中，同时从存储器的另一部分读取数据到输出总线上。 阵列中的内存元素部分包括半页。 存储器包括两个部分，每个部分具有半页存储器元件，并且进位输出在从阵列的最后半页从存储器中读取数据到输出总线之前产生进位信号。 来自上一个半页的数据被读取到输出总线上，而来自下一个下游存储器阵列的前半页的数据被加载到其存储器中。