公开(公告)号：US07626882B2

公开(公告)日：2009-12-01

申请号：US11613383

申请日：2006-12-20

申请人： Nian Yang ,  Yonggang Wu ,  Aaron Lee ,  Wei Daisy Cai

发明人： Nian Yang ,  Yonggang Wu ,  Aaron Lee ,  Wei Daisy Cai

IPC分类号： G11C5/14

CPC分类号： G11C16/12

摘要： A semiconductor memory device (104) selectably connectable to an external high voltage power supply (122) is provided. The semiconductor memory device (104) includes a switch (314), a detector (316) and a timing device (318). The switch (314) is connected to external voltage supply signals and selectably couples the external voltage supply signals to memory cells (305) of the semiconductor memory device (104) for memory operations thereof. The external voltage supply signals including a high voltage signal (412) provided from the external high voltage power supply (122) and an operational voltage signal Vcc (402). The detector (316) is connected to the external voltage supply signals for generating a timer activation signal (404) in response to detecting an operational voltage power-on period. The timing device (318) signals the switch (314) to decouple the high voltage signal (412) and the operational voltage signal (402) from the memory cells (305) in response to the timer activation signal (404) and to recouple the high voltage signal (412) and the operational voltage signal (402) to the memory cells (305) a time delay interval thereafter. The time delay interval is determined in response to the high voltage signal (412).

摘要翻译： 提供可选择地连接到外部高压电源（122）的半导体存储器件（104）。 半导体存储器件（104）包括开关（314），检测器（316）和定时装置（318）。 开关（314）连接到外部电压源信号，并且可选择地将外部电压供应信号耦合到半导体存储器件（104）的存储单元（305），用于存储器操作。 包括从外部高压电源（122）提供的高电压信号（412）的外部电压供给信号和操作电压信号Vcc（402）。 检测器（316）连接到外部电压源信号，以响应于检测到工作电压通电周期而产生定时器激活信号（404）。 定时装置（318）响应于定时器启动信号（404），向开关314通知高压信号412和操作电压信号402与存储单元305的耦合， 高电压信号（412）和操作电压信号（402）到其后的时间延迟区间。 响应于高电压信号确定时间延迟间隔（412）。

公开(公告)号：US20080151639A1

公开(公告)日：2008-06-26

申请号：US11613383

申请日：2006-12-20

申请人： Nian Yang ,  Yonggang Wu ,  Aaron Lee ,  Wei Daisy Cai

发明人： Nian Yang ,  Yonggang Wu ,  Aaron Lee ,  Wei Daisy Cai

IPC分类号： G11C16/32

CPC分类号： G11C16/12

摘要： A semiconductor memory device (104) selectably connectable to an external high voltage power supply (122) is provided. The semiconductor memory device (104) includes a switch (314), a detector (316) and a timing device (318). The switch (314) is connected to external voltage supply signals and selectably couples the external voltage supply signals to memory cells (305) of the semiconductor memory device (104) for memory operations thereof. The external voltage supply signals including a high voltage signal (412) provided from the external high voltage power supply (122) and an operational voltage signal Vcc (402). The detector (316) is connected to the external voltage supply signals for generating a timer activation signal (404) in response to detecting an operational voltage power-on period. The timing device (318) signals the switch (314) to decouple the high voltage signal (412) and the operational voltage signal (402) from the memory cells (305) in response to the timer activation signal (404) and to recouple the high voltage signal (412) and the operational voltage signal (402) to the memory cells (305) a time delay interval thereafter. The time delay interval is determined in response to the high voltage signal (412).

摘要翻译： 提供可选择地连接到外部高压电源（122）的半导体存储器件（104）。 半导体存储器件（104）包括开关（314），检测器（316）和定时装置（318）。 开关（314）连接到外部电压源信号，并且可选择地将外部电压供应信号耦合到半导体存储器件（104）的存储单元（305），用于存储器操作。 包括从外部高压电源（122）提供的高电压信号（412）的外部电压供给信号和操作电压信号Vcc（402）。 检测器（316）连接到外部电压源信号，以响应于检测到工作电压通电周期而产生定时器激活信号（404）。 定时装置（318）响应于定时器启动信号（404），向开关314通知高压信号412和操作电压信号402与存储单元305的耦合， 高电压信号（412）和操作电压信号（402）到其后的时间延迟区间。 响应于高电压信号确定时间延迟间隔（412）。

公开(公告)号：US07196938B1

公开(公告)日：2007-03-27

申请号：US11229530

申请日：2005-09-20

申请人： Yonggang Wu ,  Guowei Wang ,  Nian Yang ,  Aaron Lee

发明人： Yonggang Wu ,  Guowei Wang ,  Nian Yang ,  Aaron Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/12

摘要： A non-volatile memory cell array, such as a Flash NOR array, is programmed by applying voltages to bit lines that connect to memory cells in the memory cell array. A first bit line corresponding to a first memory cell in the memory array may be turned on to perform a first programming operation for the first memory cell and second bit line corresponding to a second memory cell in the memory array may be turned on to perform a second programming operation that is configured to complete after the first programming operation. The turning on/off of the first and second bit lines may be overlapped to share charge between the first and second bit lines. This overlapping can reduce wasted power and decrease programming pulse overshoot problems.

摘要翻译： 诸如闪存NOR阵列的非易失性存储单元阵列通过将电压施加到连接到存储单元阵列中的存储单元的位线来编程。 对应于存储器阵列中的第一存储器单元的第一位线可以被接通以对第一存储器单元执行第一编程操作，并且可以打开与存储器阵列中的第二存储器单元相对应的第二位线来执行 第二编程操作被配置为在第一编程操作之后完成。 第一和第二位线的导通/截止可以重叠以在第一和第二位线之间共享电荷。 这种重叠可以减少浪费的功率并减少编程脉冲过冲问题。

公开(公告)号：US08462564B1

公开(公告)日：2013-06-11

申请号：US13090981

申请日：2011-04-20

申请人： Yonggang Wu ,  Guowei Wang ,  Nian Yang ,  Sachit Chandra ,  Aaron Lee

发明人： Yonggang Wu ,  Guowei Wang ,  Nian Yang ,  Sachit Chandra ,  Aaron Lee

IPC分类号： G11C7/12 ,  G11C8/08 ,  G11C8/12 ,  G11C16/12

CPC分类号： G11C16/12 ,  G11C5/145 ,  G11C8/08

摘要： A non-volatile memory device includes an array of non-volatile memory cells. When programming the memory cells, a voltage supply source is used that includes multiple independent charge pumps. The independent charge pumps supply the programming voltage to different ones of bit lines in the array of memory cells. Using multiple charge pumps tends to reduce output voltage fluctuations and thereby reduce power loss.

摘要翻译： 非易失性存储器件包括非易失性存储器单元阵列。 当对存储器单元进行编程时，使用包括多个独立电荷泵的电压源。 独立电荷泵将编程电压提供给存储器单元阵列中的不同位线。 使用多个电荷泵倾向于降低输出电压波动，从而降低功率损耗。

公开(公告)号：US07352626B1

公开(公告)日：2008-04-01

申请号：US11212614

申请日：2005-08-29

申请人： Yonggang Wu ,  Guowei Wang ,  Nian Yang ,  Aaron Lee

发明人： Yonggang Wu ,  Guowei Wang ,  Nian Yang ,  Aaron Lee

IPC分类号： G11C11/34 ,  G11C7/00

CPC分类号： G11C5/14

摘要： A voltage regulator may include an operational-amplifier section, a capacitor connected to an output of the operational-amplifier section, and a switch configured to connect the capacitor to a voltage supply. The switch is configured to charge the capacitor before activating the operational-amplifier section. The capacitor is configured to store charge to supplement current being supplied from the operational-amplifier section. The voltage regulator may be used to supply power to non-volatile memory cells.

摘要翻译： 电压调节器可以包括运算放大器部分，连接到运算放大器部分的输出的电容器和被配置为将电容器连接到电压源的开关。 开关被配置为在激活运算放大器部分之前对电容器充电。 电容器被配置为存储电荷以补充从运算放大器部分提供的电流。 电压调节器可以用于向非易失性存储单元供电。

公开(公告)号：US07957204B1

公开(公告)日：2011-06-07

申请号：US11229667

申请日：2005-09-20

申请人： Yonggang Wu ,  Guowei Wang ,  Nian Yang ,  Sachit Chandra ,  Aaron Lee

发明人： Yonggang Wu ,  Guowei Wang ,  Nian Yang ,  Sachit Chandra ,  Aaron Lee

IPC分类号： G11C7/12 ,  G11C8/08 ,  G11C8/12 ,  G11C16/12

CPC分类号： G11C16/12 ,  G11C5/145 ,  G11C8/08

摘要： A non-volatile memory device includes an array of non-volatile memory cells. When programming the memory cells, a voltage supply source is used that includes multiple independent charge pumps. The independent charge pumps supply the programming voltage to different ones of bit lines in the array of memory cells. Using multiple charge pumps tends to reduce output voltage fluctuations and thereby reduce power loss.

摘要翻译： 非易失性存储器件包括非易失性存储器单元阵列。 当对存储器单元进行编程时，使用包括多个独立电荷泵的电压源。 独立电荷泵将编程电压提供给存储器单元阵列中的不同位线。 使用多个电荷泵倾向于降低输出电压波动，从而降低功率损耗。

公开(公告)号：US07948820B2

公开(公告)日：2011-05-24

申请号：US11951262

申请日：2007-12-05

申请人： Tien-Chun Yang ,  Yonggang Wu ,  Nian Yang

发明人： Tien-Chun Yang ,  Yonggang Wu ,  Nian Yang

IPC分类号： G11C7/00

CPC分类号： G11C16/30 ,  G11C7/12 ,  G11C16/24

摘要： Commonly, read times of a memory line are slowed due to voltage overshoot and/or voltage undershoot. To eliminate these problems, a control component can manage voltage while a leakage component manages timing of voltage. This allows for a line pre-charge that produces increase read times. The control component can implement as a variable resistor that modifies value to compensate for temperature. The leakage component can include a capacitor configuration that allows voltage to pass.

摘要翻译： 通常，存储线的读取时间由于电压过冲和/或电压下冲而变慢。 为了消除这些问题，控制部件可以管理电压，同时泄漏部件管理电压的时序。 这允许产生增加读取时间的线路预充电。 控制组件可以实现一个可变电阻器来修改值来补偿温度。 泄漏部件可以包括允许电压通过的电容器配置。

公开(公告)号：US20080266926A1

公开(公告)日：2008-10-30

申请号：US11741996

申请日：2007-04-30

申请人： Nian Yang ,  Yonggang Wu ,  Tien-Chun Yang

发明人： Nian Yang ,  Yonggang Wu ,  Tien-Chun Yang

IPC分类号： G11C5/06

CPC分类号： G11C8/12 ,  G11C7/12 ,  G11C7/18 ,  G11C16/24 ,  G11C2207/002

摘要： Manners for transferring information within a flash memory device across a memory array are described. A controller retrieves information from a storage unit and then a decoder decodes the information. The information is set across a series of bitlines through a pass gate to a second controller. The bitlines are both associated with the storage unit as well as bitlines associated with other storage units. A series of transistors is associated with each bitline. Different transistors are active based on if the bitlines are associated with the currently used storage unit.

摘要翻译： 描述了通过存储器阵列在闪速存储器件内传送信息的方式。 控制器从存储单元检索信息，然后解码器解码该信息。 信息通过一个通过门到一个第二个控制器的一系列位线设置。 位线都与存储单元相关联，以及与其他存储单元相关联的位线。 一系列晶体管与每个位线相关联。 基于如果位线与当前使用的存储单元相关联，不同的晶体管是有效的。

公开(公告)号：US20080130371A1

公开(公告)日：2008-06-05

申请号：US11950811

申请日：2007-12-05

申请人： Nian Yang ,  Boon-Aik Ang ,  Yonggang Wu ,  Guowei Wang ,  Fan Wan Lai

发明人： Nian Yang ,  Boon-Aik Ang ,  Yonggang Wu ,  Guowei Wang ,  Fan Wan Lai

IPC分类号： G11C16/12 ,  G11C16/28

CPC分类号： G11C7/1039 ,  G11C8/08 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/08 ,  G11C16/30 ,  G11C2207/2245

摘要： A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells (200) of a semiconductor memory device (100). A high voltage generator (106) during program or erase operations provides a continuous high voltage level (702) on selected word lines (502) and maintains a continuous high voltage level supply to a bit line decoder (120) which sequentially provides the high voltage level (706) to a first portion of bit lines (504) and discharges (708) those bit lines (504) before providing the high voltage level to a second portion (710). For additional improvements to program operations, the high voltage generator (106) decouples high voltages provided to the word lines (502) and the bit lines (504) by providing a current flow control device (1208) therebetween and provides a boosting voltage at a time (1104) to overcome a voltage level drop (1102) resulting from a capacitor load associated with selected bit lines (504) and/or the bit line decoder (120) precharges (1716) a second portion of the bit lines (504) while providing a high voltage level to a first portion to program (1706) a first portion of memory cells (200). For improvements to read operations, whether dynamic reference cells (2002) are blank is determined by providing non-identically regulated high voltage levels from a first voltage source (2112) to the dynamic reference cells (2002) and from a second voltage source (2104) to static reference cells (2004) and, if the dynamic reference cells (2002) are not blank, reads selected memory cells (200) by providing identically regulated high voltage levels to the selected memory cells (200), the dynamic reference cells (2002) and the static reference cells (2004).

公开(公告)号：US20070286006A1

公开(公告)日：2007-12-13

申请号：US11423645

申请日：2006-06-12

申请人： Yonggang Wu ,  Nian Yang ,  Boon-Aik Ang

发明人： Yonggang Wu ,  Nian Yang ,  Boon-Aik Ang

IPC分类号： G11C5/14

CPC分类号： G11C5/145

摘要： A method and apparatus are provided for improved noise reduction from switching on and off drain pumps (202) in a high voltage generator. The drain pumps (202) are divided into groups (204) and activation of the groups (204) of drain pumps (202) is staggered (304, 310). In addition, when drain pumps are switched on and off for power conservation or to maintain a steady state high voltage level, the groups (204) of drain pumps (202) are switched on and off in response to various predetermined high voltage levels (410, 412, 414, 416), with different voltage levels for different groups (204) of drain pumps (202).

摘要翻译： 提供了一种方法和装置，用于从高压发生器中的接通和关闭排放泵（202）的开关中减少噪音。 排水泵（202）被分成组（204），并且排水泵（202）的组（204）的活动是交错的（304,310）。 此外，当排水泵被接通和关闭以进行节能或保持稳定状态的高电压电平时，排水泵（202）的组（204）响应于各种预定的高电压电平（410）被接通和断开 ，412,414,416），具有用于不同组（204）排水泵（202）的不同电压电平。