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公开(公告)号：US20130159587A1
公开(公告)日：2013-06-20
申请号：US13326663
申请日：2011-12-15
IPC分类号： G06F13/36
CPC分类号： G11C29/702 , G11C5/063
摘要： A multi-interconnect integrated circuit device includes an input/output (I/O) circuit for conveying a plurality of interleaved data channel groups by configuring the I/O circuit to convey a first data channel group over a default fixed interconnect signal paths if there are no connection failures in the default fixed interconnect signal paths, and to convey the first data channel group over a second plurality of default fixed interconnect signal paths if there is at least one connection failure in the first plurality of default fixed interconnect signal paths, where the second plurality of default fixed interconnect signal paths includes a redundant fixed interconnect signal path for replacing a failed interconnect signal path from the first plurality of default fixed interconnect signal paths.
摘要翻译： 多互连集成电路装置包括用于通过配置I / O电路来输送多个交错数据信道组的输入/输出（I / O）电路，以在默认的固定互连信号路径上传送第一数据信道组，如果 在默认固定互连信号路径中没有连接故障，并且如果在第一多个默认固定互连信号路径中存在至少一个连接故障，并且在第二多个默认固定互连信号路径上传送第一数据信道组，其中 所述第二多个默认固定互连信号路径包括用于从所述第一多个默认固定互连信号路径替换故障互连信号路径的冗余固定互连信号路径。
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公开(公告)号：US08909840B2
公开(公告)日：2014-12-09
申请号：US13330482
申请日：2011-12-19
IPC分类号： G06F13/28
CPC分类号： G06F13/4273 , Y02D10/14 , Y02D10/151
摘要： Techniques are disclosed relating to data inversion encoding. In one embodiment, an apparatus includes an interface circuit. The interface circuit is configured to perform first and second data bursts that include respective pluralities of data transmissions encoded using an inversion coding scheme. In such an embodiment, the initial data transmission of the second data burst is encoded using the final data transmission of the first data burst. In some embodiments, the first and second data bursts correspond to successive write operations or successive read operations to a memory module from a memory PHY.
摘要翻译： 公开了涉及数据反转编码的技术。 在一个实施例中，一种装置包括接口电路。 接口电路被配置为执行包括使用反转编码方案编码的相应多个数据传输的第一和第二数据突发。 在这样的实施例中，使用第一数据突发的最终数据传输对第二数据脉冲串的初始数据传输进行编码。 在一些实施例中，第一和第二数据脉冲串对应于来自存储器PHY的存储器模块的连续写操作或连续读操作。
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公开(公告)号：US20130159584A1
公开(公告)日：2013-06-20
申请号：US13330482
申请日：2011-12-19
IPC分类号： G06F13/28
CPC分类号： G06F13/4273 , Y02D10/14 , Y02D10/151
摘要： Techniques are disclosed relating to data inversion encoding. In one embodiment, an apparatus includes an interface circuit. The interface circuit is configured to perform first and second data bursts that include respective pluralities of data transmissions encoded using an inversion coding scheme. In such an embodiment, the initial data transmission of the second data burst is encoded using the final data transmission of the first data burst. In some embodiments, the first and second data bursts correspond to successive write operations or successive read operations to a memory module from a memory PHY.
摘要翻译： 公开了涉及数据反转编码的技术。 在一个实施例中，一种装置包括接口电路。 接口电路被配置为执行包括使用反转编码方案编码的相应多个数据传输的第一和第二数据突发。 在这样的实施例中，使用第一数据突发的最终数据传输对第二数据脉冲串的初始数据传输进行编码。 在一些实施例中，第一和第二数据脉冲串对应于来自存储器PHY的存储器模块的连续写操作或连续读操作。
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公开(公告)号：US08330766B1
公开(公告)日：2012-12-11
申请号：US12340496
申请日：2008-12-19
申请人： David Kirk McAllister , Steven E. Molnar , Jerome F. Duluk, Jr. , Emmett M. Kilgariff , Patrick R. Brown , Christian Johannes Amsinck , James Michael O'Connor , John Matthew Burgess , Gregory Alan Muthler , James Robertson
发明人： David Kirk McAllister , Steven E. Molnar , Jerome F. Duluk, Jr. , Emmett M. Kilgariff , Patrick R. Brown , Christian Johannes Amsinck , James Michael O'Connor , John Matthew Burgess , Gregory Alan Muthler , James Robertson
CPC分类号： G09G5/39 , G09G5/363 , G09G2360/06 , G09G2360/121 , G09G2360/122
摘要： A system and method for performing zero-bandwidth-clears reduces external memory accesses by a graphics processor when performing clears and subsequent read operations. A set of clear values is stored in the graphics processor. Each region of a color or z buffer may be configured using a zero-bandwidth-clear command to reference a clear value without writing the external memory. The clear value is provided to a requestor without accessing the external memory when a read access is performed.
摘要翻译： 执行零带宽清除的系统和方法在执行清除和后续读取操作时减少图形处理器的外部存储器访问。 一组清晰的值存储在图形处理器中。 可以使用零带宽清除命令来配置颜色或z缓冲区的每个区域以引用清除值而不写入外部存储器。 当执行读取访问时，清除值被提供给请求者而不访问外部存储器。
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公开(公告)号：US06725308B2
公开(公告)日：2004-04-20
申请号：US10288393
申请日：2002-11-05
IPC分类号： G06F946
CPC分类号： G06F9/52 , G06F9/3004 , G06F9/30087
摘要： A computer processor includes a number of register pairs LOCKADD/LOCKCOUNT to hold values identifying when a computer resource is locked. The LOCKCOUNT register is incremented or decremented in response to lock or unlock instructions, respectively. The lock is freed when a count associated with the LOCKCOUNT register is decremented to zero. In embodiments without LOCKOUT registers, the lock may be freed on any unlock instruction corresponding to the lock. In some embodiments, a computer object includes a header in which two header LSBs store: (1) a LOCK bit indicating whether the object is locked, and (2) a WANT bit indicating whether a thread is waiting to acquire a lock for the object.
摘要翻译： 计算机处理器包括多个寄存器对LOCKADD / LOCKCOUNT以保存识别计算机资源何时被锁定的值。 响应锁定或解锁指令，LOCKCOUNT寄存器分别递增或递减。 当与LOCKCOUNT寄存器关联的计数递减为零时，该锁定被释放。 在没有LOCKOUT寄存器的实施例中，锁可以在对应于锁的任何解锁指令上被释放。 在一些实施例中，计算机对象包括头部，其中两个标题LSB存储：（1）指示对象是否被锁定的LOCK位，以及（2）指示线程是否正在等待获取对象的锁的WANT位 。
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6.发明授权Array access boundary check by executing BNDCHK instruction with comparison specifiers 有权通过执行BNDCHK指令与比较说明符进行阵列访问边界检查公开(公告)号：US06408383B1
公开(公告)日：2002-06-18
申请号：US09565625
申请日：2000-05-04
IPC分类号： G06F1206
CPC分类号： G06F9/30021 , G06F9/30003
摘要： The present invention provides a method and apparatus for executing a boundary check instruction that provides accelerated bound checking. The instruction can be used to determine whether an array address represents a null pointer, and whether an array index is less than zero or greater than the size of the array. Three extensions of a boundary check instruction are provided, with each performing a different combination of three boundary check comparisons. One comparison compares a first operand, which may contain the base address of an array, to zero. Another comparison evaluates the value of a second operand, which may contain an index offset, to determine if it is less than zero. The other comparison evaluates whether the value of the second operand is greater than or equal to a third operand. The third operand may indicate the size of an array. A trap is generated if any of the comparisons evaluates to true.
摘要翻译： 本发明提供了一种用于执行提供加速绑定检查的边界检查指令的方法和装置。 该指令可用于确定阵列地址是否表示空指针，以及数组索引是否小于零或大于数组的大小。 提供了边界检查指令的三个扩展，每个执行三个边界检查比较的不同组合。 一个比较将可能包含数组的基地址的第一个操作数与零进行比较。 另一个比较评估第二个操作数的值，该值可以包含索引偏移量，以确定它是否小于零。 另一个比较评估第二个操作数的值是否大于或等于第三个操作数。 第三个操作数可以指示数组的大小。 如果任何比较评估为true，则会生成陷阱。
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7.发明授权Replicating code to eliminate a level of indirection during execution of an object oriented computer program 失效在执行面向对象的计算机程序期间复制代码以消除间接级别
公开(公告)号：US5970242A
公开(公告)日：1999-10-19
申请号：US787846
申请日：1997-01-23
CPC分类号： G06F9/30174 , G06F9/4425 , G06F9/443 , G06F9/44589 , G06F9/45504 , G06F2212/451
摘要： A method and apparatus for accelerating the execution of an object oriented computer program having a plurality of objects. In one embodiment, each of the objects includes an object header and object data which are stored in a memory. Moreover, each of the objects is associated with a corresponding set of methods (or functions). A typical object oriented program only maintains one copy of a method which is accessed by more than one object. However, in the present invention, each method is copied and stored in a memory, such that each object has a dedicated set of methods stored in memory. For example, if a first object and a second object require access to the same method, then a first copy of this method is provided for the first object, and a second copy of this method is provided for the second object. Providing each object with a dedicated set of methods minimizes the levels of indirection required to access the methods, and thereby accelerates the execution of instructions which access the objects.
摘要翻译： 一种用于加速具有多个对象的面向对象的计算机程序的执行的方法和装置。 在一个实施例中，每个对象包括存储在存储器中的对象标题和对象数据。 此外，每个对象与一组相应的方法（或功能）相关联。 一个典型的面向对象程序只保存一个由多个对象访问的方法的一个副本。 然而，在本发明中，将每种方法复制并存储在存储器中，使得每个对象具有存储在存储器中的专用方法集合。 例如，如果第一对象和第二对象需要访问相同的方法，则为第一对象提供该方法的第一副本，并且为第二对象提供该方法的第二副本。 通过专门的方法为每个对象提供访问方法所需的间接级别最小化，从而加速访问对象的指令的执行。
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8.发明授权Bounded-pause time garbage collection system and method including read and write barriers associated with an instance of a partially relocated object 失效有界暂停时间垃圾收集系统和方法，包括与部分重定位对象的实例相关联的读写障碍
公开(公告)号：US5857210A
公开(公告)日：1999-01-05
申请号：US882801
申请日：1997-06-26
申请人： Marc Tremblay , James Michael O'Connor , Guy L. Steele, Jr. , Sanjay Vishin , Ole Agesen , Steven Heller , Derek R. White
发明人： Marc Tremblay , James Michael O'Connor , Guy L. Steele, Jr. , Sanjay Vishin , Ole Agesen , Steven Heller , Derek R. White
CPC分类号： G06F12/0269 , G06F12/0276 , Y10S707/99957
摘要： A partially relocated object identifier store including "copy from" and "copy to" identifier storage accessible to write and read barrier logic allows the write and read barrier logic to selectively direct store- and load-oriented accesses to an appropriate FromSpace or ToSpace instance of a partially relocated memory object, in accordance with the memory object's partial relocation state. In some embodiments, the barriers trap to a partially relocated object trap handler. In other embodiments, the write barrier itself directs accesses without software trap handler overheads. Optional "how far" indication storage facilitates differentiation by the barrier logic, or by the partially relocated object trap handler, between a copied portion and an uncopied portion of the partially relocated memory object.
摘要翻译： 包含从写入和读取屏障逻辑访问的“复制到”和“复制到”标识符存储器的部分重新定位的对象标识符存储允许写入和读取屏障逻辑选择性地将存储和负载导向的访问定向到适当的FromSpace或ToSpace实例 根据存储器对象的部分重定位状态，部分重新定位的存储器对象。 在一些实施例中，障碍物捕获到部分重定位的对象陷阱处理器。 在其他实施例中，写入屏障本身引导访问而不需要软件陷阱处理程序开销。 可选的“多远”指示存储有助于通过屏障逻辑或部分重新定位的对象陷阱处理器在部分重新定位的存储器对象的复制部分和未覆盖部分之间进行区分。
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9.发明授权Method and system for rapid insertion of various data streams into sorted tree structures 失效将各种数据流快速插入分类树结构的方法和系统公开(公告)号：US07016904B1
公开(公告)日：2006-03-21
申请号：US09842387
申请日：2001-04-25
IPC分类号： G06F17/30
CPC分类号： G06F17/30961 , Y10S707/99937 , Y10S707/99942 , Y10S707/99943 , Y10S707/99952 , Y10S707/99953
摘要： The present invention provides the method and system that redistribute the nodes of a sorted tree to enable faster data insertion. Further, the tree typically contains a fixed number of levels, each comprising a fixed number of nodes. Each node in the tree is indexed and each leaf node may comprise a number of data segments. An increment is empirically calculated as space redistributed among non-empty leaf nodes. Furthermore, when a data segment is inserted and certain conditions are met, a data structure with a marked head and tail effectively “traverses” the tree from one end to the other searching for empty leaf nodes. In cases where the data structure encounters an empty leaf node, the data structure continues traversing unless empirically determined conditions stipulate that the process halts until the next data segment insertion before continuing. Moreover, in cases where the data structure encounters a non-empty leaf node, the contents of the node are copied from the head to the tail of the data structure. When the node has been copied, the data structure updates the tree to ensure that a lookup operation on the copied node remains valid and that the invariants of the tree hold before and after the redistribution. Furthermore, the contents in the head of the data structure are then deleted and the tail advanced to leave an increment amount of empty spaces in the traveling direction. The traversal process may then follow one of two possible paths of action: either continue traversing the tree or halt for the next data insertion before continuing.
摘要翻译： 本发明提供了重新分配排序树的节点以使更快的数据插入的方法和系统。 此外，树通常包含固定数量的级别，每个级别包括固定数量的节点。 索引树中的每个节点，并且每个叶节点可以包括多个数据段。 经验计算的增量是在非空叶节点之间重新分配的空间。 此外，当插入数据段并满足某些条件时，具有标记的头和尾的数据结构从一端有效地“遍历”树到另一端搜索空叶节点。 在数据结构遇到空叶节点的情况下，数据结构将继续遍历，除非经验确定的条件规定该过程在继续之前停止下一个数据段插入。 此外，在数据结构遇到非空叶节点的情况下，节点的内容从头到尾复制到数据结构的尾部。 当节点被复制时，数据结构更新树，以确保复制节点上的查找操作保持有效，并且重新分配之前和之后树的不变量保持不变。 此外，数据结构的头部的内容然后被删除，并且尾部前进以在行进方向上留下空白空间的增量。 然后，遍历过程可以遵循两个可能的动作路径之一：继续遍历树或停止下一次数据插入。
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10.发明授权Ternary content addressable memory based multi-dimensional multi-way branch selector and method of operating same 失效三元内容可寻址存储器多维多路分支选择器及其操作方法公开(公告)号：US06988189B1
公开(公告)日：2006-01-17
申请号：US09703337
申请日：2000-10-31
CPC分类号： G06F9/30058 , G06F9/30021 , G06F9/3806 , G06F9/3844
摘要： An embodiment of the present invention described and shown in the specification and drawing is a Ternary Content Addressable Memory (TCAM) multi-dimensional multi-way branch selector. The embodiment that is disclosed includes a wide TCAM and a pre-TCAM multi-field multi-mode comparator for coupling to a microprocessor for performing multi-way branching decisions based on multi-dimensional comparisons. It is emphasized that this abstract is provided to comply with the rule requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
摘要翻译： 在说明书和附图中描述和示出的本发明的实施例是三元内容可寻址存储器（TCAM）多维多路分支选择器。 所公开的实施例包括宽TCAM和用于耦合到微处理器的前TCAM多场多模式比较器，用于基于多维比较执行多路分支决定。 要强调的是，该摘要被提供以符合要求抽象的规则，这将允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。
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