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公开(公告)号：US06529982B2
公开(公告)日：2003-03-04
申请号：US09296705
申请日：1999-04-21
IPC分类号： G06F946
CPC分类号： G06F9/52 , G06F9/3004 , G06F9/30087
摘要： A computer processor includes a number of register pairs LOCKADDR/LOCKCOUNT. In each pair, the LOCKADDR/LOCKCOUNT register is to hold a value that identifies a lock for a computer resource. When a lock instruction issues, the corresponding LOCKCOUNT register is incremented. When an unlock instruction issues, the corresponding LOCKCOUNT register is decremented. The lock is freed when a count associated with the LOCKCOUNT register is decremented to zero. This scheme provides fast locking and unlocking in many frequently occurring situations. In some embodiments, the LOCKCOUNT registers are omitted, and the lock is freed on any unlock instruction corresponding to the lock. In some embodiments, a computer object includes a header which includes a pointer to a class structure. The class structure is aligned on a 4-byte boundary, and therefore two LSBs of the pointer to the class structure are zero and are not stored in the header. Instead, two header LSBs store: (1) a LOCK bit indicating whether the object is locked, and (2) a WANT bit indicating whether a thread is waiting to acquire a lock for the object.
摘要翻译： 计算机处理器包括多个寄存器对LOCKADDR / LOCKCOUNT。 在每一对中，LOCKADDR / LOCKCOUNT寄存器将保存标识计算机资源的锁的值。 当锁定指令发生时，相应的LOCKCOUNT寄存器增加。 当解锁指令发生时，相应的LOCKCOUNT寄存器递减。 当与LOCKCOUNT寄存器关联的计数递减为零时，该锁定被释放。 该方案在许多频繁发生的情况下提供快速锁定和解锁。 在一些实施例中，省略LOCKCOUNT寄存器，并且在与锁相对应的任何解锁指令上释放锁。 在一些实施例中，计算机对象包括包括指向类结构的指针的报头。 类结构在4字节边界上对齐，因此指向类结构的指针的两个LSB为零，不存储在标题中。 相反，两个标题LSB存储：（1）指示对象是否被锁定的LOCK位，以及（2）指示线程是否正在等待获取对象的锁的WANT位。
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公开(公告)号：US5968157A
公开(公告)日：1999-10-19
申请号：US788808
申请日：1997-01-23
IPC分类号： G06F9/46
CPC分类号： G06F9/52 , G06F9/3004 , G06F9/30087
摘要： A computer processor includes a number of register pairs LOCKADDR/LOCKCOUNT. In each pair, the LOCKADDR/LOCKCOUNT register is to hold a value that identifies a lock for a computer resource. When a lock instruction issues, the corresponding LOCKCOUNT register is incremented. When an unlock instruction issues, the corresponding LOCKCOUNT register is decremented. The lock is freed when a count associated with the LOCKCOUNT register is decremented to zero. This scheme provides fast locking and unlocking in many frequently occurring situations. In some embodiments, the LOCKCOUNT registers are omitted, and the lock is freed on any unlock instruction corresponding to the lock. In some embodiments, a computer object includes a header which includes a pointer to a class structure. The class structure is aligned on a 4-byte boundary, and therefore two LSBs of the pointer to the class structure are zero and are not stored in the header. Instead, two header LSBs store: (1) a LOCK bit indicating whether the object is locked, and (2) a WANT bit indicating whether a thread is waiting to acquire a lock for the object.
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公开(公告)号：US6021469A
公开(公告)日：2000-02-01
申请号：US788807
申请日：1997-01-23
IPC分类号： G06F9/30 , G06F9/318 , G06F9/34 , G06F9/345 , G06F9/40 , G06F9/42 , G06F9/445 , G06F9/455 , G06F12/08 , G06F12/00 , G06F13/00
CPC分类号： G06F9/30021 , G06F12/0875 , G06F9/30134 , G06F9/30174 , G06F9/30181 , G06F9/345 , G06F9/3879 , G06F9/4425 , G06F9/443 , G06F9/44589 , G06F9/45504 , G06F2212/451 , Y02B60/1225
摘要： A hardware virtual machine instruction processor directly executes virtual machine instructions that are processor architecture independent. The hardware processor has high performance; is low cost; and exhibits low power consumption. The hardware processor is well suited for portable applications. These applications include, for example, an Internet chip for network appliances, a cellular telephone processor, other telecommunications integrated circuits, or other low-power, low-cost applications such as embedded processors, and portable devices.
摘要翻译： 硬件虚拟机指令处理器直接执行独立于处理器架构的虚拟机指令。 硬件处理器性能高; 成本低廉 并具有低功耗。 硬件处理器非常适合便携式应用。 这些应用包括例如用于网络设备的因特网芯片，蜂窝电话处理器，其他电信集成电路或其他低功耗，低成本的应用，例如嵌入式处理器和便携式设备。
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公开(公告)号：US6014723A
公开(公告)日：2000-01-11
申请号：US786352
申请日：1997-01-23
IPC分类号： G06F11/28 , G06F9/30 , G06F9/318 , G06F9/345 , G06F9/40 , G06F9/42 , G06F9/445 , G06F9/45 , G06F9/455 , G06F12/08 , G06F12/14 , G06F17/30
CPC分类号： G06F9/30021 , G06F12/0875 , G06F12/1441 , G06F9/264 , G06F9/30134 , G06F9/30174 , G06F9/345 , G06F9/4425 , G06F9/443 , G06F9/44589 , G06F9/45504 , G06F2212/451
摘要： An array boundary checking apparatus is configured to verify that a referenced element of an information array is within a maximum array size boundary value and a minimum array size boundary value. The array boundary checking apparatus of the invention includes an associative memory element that stores and retrieves a plurality of array bound values. Each one of the plurality of array bound values is associated with one of the plurality of array access instructions. An input section simultaneously compares the array access instruction identifier with at least a portion of each of the stored array reference entries, wherein the array access instruction identifier identifies an array access instruction. An output section is configured to provide as an array bounds output values one of the plurality of array bound values stored in one of the plurality of memory locations of the associated memory element. A first comparison element compares the value of the referenced element and the maximum array index boundary value and provides a maximum violation signal if the value of the element is greater than the maximum array size boundary value. A second comparison element compares the value of the element and the minimum array size boundary value and provides a minimum violation signal if the value of the element is less than the minimum array bounds value. Either a maximum violation signal or a minimum violation signal results in an exception.
摘要翻译： 阵列边界检查装置被配置为验证信息数组的引用元素在最大数组大小边界值和最小数组大小边界值内。 本发明的阵列边界检查装置包括存储和检索多个阵列限定值的关联存储元件。 多个阵列绑定值中的每一个与多个阵列访问指令之一相关联。 输入部分同时将数组访问指令标识符与每个存储的数组参考条目的至少一部分进行比较，其中数组访问指令标识符标识数组访问指令。 输出部分被配置为提供作为阵列限定存储在相关联的存储器元件的多个存储器位置之一中的多个阵列约束值之一的输出值。 第一个比较元素比较引用元素的值和最大数组索引边界值，如果元素的值大于最大数组大小边界值，则提供最大违规信号。 第二比较元素比较元素的值和最小数组大小边界值，并且如果元素的值小于最小数组边界值，则提供最小违规信号。 最大违规信号或最小违规信号都会导致异常。
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公开(公告)号：US06725308B2
公开(公告)日：2004-04-20
申请号：US10288393
申请日：2002-11-05
IPC分类号： G06F946
CPC分类号： G06F9/52 , G06F9/3004 , G06F9/30087
摘要： A computer processor includes a number of register pairs LOCKADD/LOCKCOUNT to hold values identifying when a computer resource is locked. The LOCKCOUNT register is incremented or decremented in response to lock or unlock instructions, respectively. The lock is freed when a count associated with the LOCKCOUNT register is decremented to zero. In embodiments without LOCKOUT registers, the lock may be freed on any unlock instruction corresponding to the lock. In some embodiments, a computer object includes a header in which two header LSBs store: (1) a LOCK bit indicating whether the object is locked, and (2) a WANT bit indicating whether a thread is waiting to acquire a lock for the object.
摘要翻译： 计算机处理器包括多个寄存器对LOCKADD / LOCKCOUNT以保存识别计算机资源何时被锁定的值。 响应锁定或解锁指令，LOCKCOUNT寄存器分别递增或递减。 当与LOCKCOUNT寄存器关联的计数递减为零时，该锁定被释放。 在没有LOCKOUT寄存器的实施例中，锁可以在对应于锁的任何解锁指令上被释放。 在一些实施例中，计算机对象包括头部，其中两个标题LSB存储：（1）指示对象是否被锁定的LOCK位，以及（2）指示线程是否正在等待获取对象的锁的WANT位 。
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公开(公告)号：US07437534B2
公开(公告)日：2008-10-14
申请号：US11533314
申请日：2006-09-19
申请人： Marc Tremblay , William N. Joy
发明人： Marc Tremblay , William N. Joy
CPC分类号： G06F9/3891 , G06F9/30098 , G06F9/3012 , G06F9/3838 , G06F9/3853
摘要： A Very Long Instruction Word (VLIW) processor having a plurality of functional units includes a multi-ported register file that is divided into a plurality of separate register file segments, each of the register file segments being associated to one of the plurality of functional units. The register file segments are partitioned into local registers and global registers. The global registers are read and written by all functional units. The local registers are read and written only by a functional unit associated with a particular register file segment. The local registers and global registers are addressed using register addresses in an address space that is separately defined for a register file segment/functional unit pair. The global registers are addressed within a selected global register range using the same register addresses for the plurality of register file segment/functional unit pairs. The local registers in a register file segment are addressed using register addresses in a local register range outside the global register range that are assigned within a single register file segment/functional unit pair. Register addresses in the local register range are the same for the plurality of register file segment/functional unit pairs and address registers locally within a register file segment/functional unit pair.
摘要翻译： 具有多个功能单元的超长指令字（VLIW）处理器包括被分成多个单独寄存器文件段的多端口寄存器文件，每个寄存器文件段与多个功能单元之一相关联 。 寄存器文件段被划分为本地寄存器和全局寄存器。 全局寄存器由所有功能单元读写。 本地寄存器仅由与特定寄存器文件段相关联的功能单元读取和写入。 使用寄存器文件段/功能单元对分别定义的地址空间中的寄存器地址来寻址本地寄存器和全局寄存器。 使用与多个寄存器文件段/功能单元对相同的寄存器地址，在选定的全局寄存器范围内对全局寄存器进行寻址。 寄存器文件段中的本地寄存器使用在单个寄存器文件段/功能单元对内分配的全局寄存器范围之外的本地寄存器范围中的寄存器地址进行寻址。 本地寄存器范围中的寄存器地址对于寄存器文件段/功能单元对中本地的多个寄存器文件段/功能单元对和地址寄存器是相同的。
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7.发明授权公开(公告)号：US06801997B2
公开(公告)日：2004-10-05
申请号：US10154076
申请日：2002-05-23
IPC分类号： G06F938
CPC分类号： G06F9/30141 , G06F9/30127 , G06F9/3804 , G06F9/3851 , G06F9/3885 , G06F9/4843 , G06F12/0842
摘要： A processor includes logic for tagging a thread identifier (TID) for usage with processor blocks that are not stalled. Pertinent non-stalling blocks include caches, translation look-aside buffers (TLB), a load buffer asynchronous interface, an external memory management unit (MMU) interface, and others. A processor includes a cache that is segregated into a plurality of N cache parts. Cache segregation avoids interference, “pollution”, or “cross-talk” between threads. One technique for cache segregation utilizes logic for storing and communicating thread identification (TID) bits. The cache utilizes cache indexing logic. For example, the TID bits can be inserted at the most significant bits of the cache index.
摘要翻译： 处理器包括用于标记线程标识符（TID）的逻辑，用于未被停止的处理器块的使用。 相关的非停滞块包括缓存，翻译后备缓冲器（TLB），加载缓冲器异步接口，外部存储器管理单元（MMU）接口等。 处理器包括分离成多个N个高速缓存部分的高速缓存。 缓存隔离避免线程间的干扰，“污染”或“串扰”。 用于缓存分离的一种技术利用用于存储和传送线程标识（TID）位的逻辑。 缓存使用高速缓存索引逻辑。 例如，TID位可以插入高速缓存索引的最高有效位。
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公开(公告)号：US06542991B1
公开(公告)日：2003-04-01
申请号：US09309734
申请日：1999-05-11
IPC分类号： G06F1212
CPC分类号： G06F9/30141 , G06F9/30127 , G06F9/3804 , G06F9/3851 , G06F9/3885 , G06F9/4843 , G06F12/0842
摘要： A processor includes logic for tagging a thread identifier (TID) for usage with processor blocks that are not stalled. Pertinent non-stalling blocks include caches, translation look-aside buffers (TLB), a load buffer asynchronous interface, an external memory management unit (MMU) interface, and others. A processor includes a cache that is segregated into a plurality of N cache parts. Cache segregation avoids interference, “pollution”, or “cross-talk” between threads. One technique for cache segregation utilizes logic for storing and communicating thread identification (TID) bits. The cache utilizes cache indexing logic. For example, the TID bits can be inserted at the most significant bits of the cache index.
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公开(公告)号：US06230230B1
公开(公告)日：2001-05-08
申请号：US09204794
申请日：1998-12-03
申请人： William N. Joy , James M. O'Connor , Marc Tremblay
发明人： William N. Joy , James M. O'Connor , Marc Tremblay
IPC分类号： G06F1200
CPC分类号： G06F9/52 , G06F9/3004 , G06F9/30087
摘要： Elimination of traps and atomics in thread synchronization is provided. In one embodiment, a processor includes a lock cache. The lock cache holds a value that corresponds to or identifies a computer resource only if a current thread executing on the processor owns the computer resource. A lock cache operation (e.g., a lockcachecheck instruction) determines whether a value identifying a computer resource is cached in the lock cache and returns a first predetermined value if the value identifying the computer resource is cached in the lock cache. Otherwise, a second predetermined value is returned.
摘要翻译： 提供线程同步中的陷阱和原子消除。 在一个实施例中，处理器包括锁高速缓存。 只有当处理器上执行的当前线程拥有计算机资源时，锁缓存才能保存对应于或识别计算机资源的值。 锁定高速缓存操作（例如，锁定检查指令）确定标识计算机资源的值是否被缓存在锁定缓存中，并且如果标识计算机资源的值被缓存在锁定缓存中，则返回第一预定值。 否则，返回第二预定值。
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公开(公告)号：US07316021B2
公开(公告)日：2008-01-01
申请号：US10779944
申请日：2004-02-17
CPC分类号： G06F9/4843 , G06F9/3842 , G06F9/3851 , G06F9/3861
摘要： A processor includes logic for attaining a very fast exception handling functionality while executing non-threaded programs by invoking a multithreaded-type functionality in response to an exception condition. The processor, while operating in multithreaded conditions or while executing non-threaded programs, progresses through multiple machine states during execution. The very fast exception handling logic includes connection of an exception signal line to thread select logic, causing an exception signal to evoke a switch in thread and machine state. The switch in thread and machine state causes the processor to enter and to exit the exception handler immediately, without waiting to drain the pipeline or queues and without the inherent timing penalty of the operating system's software saving and restoring of registers.
摘要翻译： 处理器包括用于通过响应于异常情况调用多线程类型功能来执行非线程程序来获得非常快速的异常处理功能的逻辑。 处理器在多线程状态下运行或执行非线程程序时，在执行过程中会经历多个机器状态。 非常快的异常处理逻辑包括将异常信号线连接到线程选择逻辑，导致异常信号引起线程和机器状态的开关。 线程和机器状态的切换使得处理器立即进入并退出异常处理程序，而不用等待排除流水线或队列，并且没有操作系统的软件保存和恢复寄存器的固有时间损失。
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