公开(公告)号：US07018884B2

公开(公告)日：2006-03-28

申请号：US10774349

申请日：2004-02-06

申请人： Adrian Berthold ,  Josef Böck ,  Jürgen Holz ,  Wolfgang Klein

发明人： Adrian Berthold ,  Josef Böck ,  Jürgen Holz ,  Wolfgang Klein

IPC分类号： H01L21/8238

CPC分类号： H01L21/8249

摘要： The present invention provides a method for parallel production of an MOS transistor in an MOS area of a substrate and a bipolar transistor in a bipolar area of the substrate. The method comprises generating an MOS preparation structure in the MOS area, wherein the MOS preparation structure comprises an area provided for a channel, a gate dielectric, a gate electrode layer and a mask layer on the gate electrode layer. Further, a bipolar preparation structure is generated in the bipolar area, which comprises a conductive layer and a mask layer on the conductive layer. The mask layer is thinned in the area of the gate electrode. For determining a gate electrode and a base terminal area, common structuring of the gate electrode layer and the conductive layer is performed.

摘要翻译： 本发明提供一种用于在基板的MOS区域和双极晶体管的基板的双极区域中并联制造MOS晶体管的方法。 该方法包括在MOS区域中产生MOS制备结构，其中MOS制备结构包括在栅极电极层上设置用于沟道的区域，栅极电介质，栅极电极层和掩模层。 此外，在双极性区域中产生双极制备结构，其在导电层上包括导电层和掩模层。 掩模层在栅电极的区域中变薄。 为了确定栅极电极和基极端子区域，执行栅电极层和导电层的共同构造。

公开(公告)号：US07285490B2

公开(公告)日：2007-10-23

申请号：US11181574

申请日：2005-07-14

申请人： Hans-Joachim Barth ,  Jürgen Holz

发明人： Hans-Joachim Barth ,  Jürgen Holz

IPC分类号： H01L21/4763

CPC分类号： H01L23/5223 ,  H01L23/53238 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/48463 ,  H01L2924/14 ,  H01L2924/00

摘要： A method for production of an integrated circuit arrangement which contains a capacitor. A dielectric layer is structured with the aid of a two-stage etching process, and with the aid of a hard mask. In the case of an electrically insulating hard mask, the hard mask is removed again. In the case of an electrically conductive hard mask, parts of the hard mask may remain in the circuit arrangement.

摘要翻译： 一种用于制造包含电容器的集成电路装置的方法。 借助于两层蚀刻工艺，借助于硬掩模来构造电介质层。 在电绝缘硬掩模的情况下，再次去除硬掩模。 在导电硬掩模的情况下，硬掩模的部分可能保留在电路装置中。

公开(公告)号：US07545016B2

公开(公告)日：2009-06-09

申请号：US11391613

申请日：2006-03-28

申请人： Jürgen Holz

发明人： Jürgen Holz

IPC分类号： H01L31/058 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L27/14636 ,  H01L27/14683

摘要： An integrated layer stack arrangement, an optical sensor and a method for producing an integrated layer stack arrangement is disclosed. Generally, an integrated layer stack arrangement includes a plurality of layer stacks arranged on top of each other, each layer stack including a metal layer and a dielectric layer arranged; at least one photodiode integrated into the plurality of layer stacks; a trench arranged above the last least one photodiode, the trench extending through at least a portion of the plurality of layer stacks so that light impinging on the plurality of layer stacks impinges on the integrated photodiode along the trench; a first passivation partial layer applied on the plurality of layer stacks; and a second passivation partial layer applied on the plurality of layer stacks and a bottom and walls of the trench.

摘要翻译： 公开了一种集成层堆叠布置，光学传感器和用于制造集成层堆叠布置的方法。 通常，集成层堆叠装置包括布置在彼此顶部的多个层堆叠，每个层堆叠包括金属层和布置的介电层; 集成到所述多个层堆叠中的至少一个光电二极管; 布置在所述最后一个光电二极管上方的沟槽，所述沟槽延伸穿过所述多个层堆叠的至少一部分，使得入射在所述多个层堆叠上的光沿着所述沟槽撞击所述集成光电二极管; 施加在所述多个层堆叠上的第一钝化部分层; 以及施加在所述多个层堆叠上的第二钝化部分层和所述沟槽的底部和壁。

公开(公告)号：US07528453B2

公开(公告)日：2009-05-05

申请号：US10530634

申请日：2003-09-19

申请人： Jürgen Holz ,  Klaus Schrüfer ,  Helmut Tews

发明人： Jürgen Holz ,  Klaus Schrüfer ,  Helmut Tews

IPC分类号： H01L27/088

CPC分类号： H01L29/66636 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/3205 ,  H01L29/0653 ,  H01L29/41783

摘要： A field-effect transistor (FET) with local source-drain insulation is described. The FET includes a semiconductor substrate, source and drain depressions, a depression insulation layer, an electrically conductive filling layer, a gate dielectric, and a gate layer. The depression insulation layer is formed at least in bottom regions of the source and drain depressions. The electrically conductive filling layer realizes source and drain regions and fills the source and drain depressions at a surface of the depression insulation layer. The gate dielectric is formed at a substrate surface between the source and drain depressions. The gate layer (is formed at a surface of the gate dielectric. The source and drain depressions have, in an upper region, a widening with a predetermined death for realizing defined channel connection regions.

摘要翻译： 描述了具有局部源极 - 漏极绝缘的场效应晶体管（FET）。 FET包括半导体衬底，源极和漏极凹陷，凹陷绝缘层，导电填充层，栅极电介质和栅极层。 凹陷绝缘层至少形成在源极和漏极凹陷的底部区域中。 导电填充层实现源极和漏极区域并填充凹陷绝缘层的表面处的源极和漏极凹陷。 栅极电介质形成在源极和漏极凹陷之间的衬底表面处。 栅极层形成在栅极电介质的表面。 源极和漏极凹陷在上部区域中具有用于实现限定的沟道连接区域的预定深度的加宽。

公开(公告)号：US07622374B2

公开(公告)日：2009-11-24

申请号：US11320489

申请日：2005-12-29

申请人： Matthias Goldbach ,  Jürgen Holz

发明人： Matthias Goldbach ,  Jürgen Holz

IPC分类号： H01L21/38 ,  H01L21/22

CPC分类号： H01L27/10894 ,  H01L21/268

摘要： Methods of fabricating an integrated circuit, in particular a dynamic random access memory are described. After forming memory cells on a semiconductor substrate a mirror layer is provided, said mirror layer covering the memory cells. Then logic devices are formed adjoining to said memory cells covered by said mirror layer, said forming of said logic devices including activating the dopants in dopant regions by means of a radiation annealing, said radiation being reflected by said mirror layer. After at least partly removing the mirror layer; a wiring of the memory cells and of the logic devices is formed.

摘要翻译： 描述了制造集成电路，特别是动态随机存取存储器的方法。 在半导体衬底上形成存储单元之后，提供镜层，所述镜层覆盖存储单元。 然后形成与所述镜层所覆盖的所述存储器单元相邻的逻辑器件，所述逻辑器件的形成包括通过辐射退火激活掺杂剂区域中的掺杂剂，所述辐射由所述镜层反射。 在至少部分地去除镜层之后; 形成存储单元和逻辑器件的布线。

公开(公告)号：US07763519B2

公开(公告)日：2010-07-27

申请号：US11205767

申请日：2005-08-16

申请人： Hans-Joachim Barth ,  Jürgen Holz

发明人： Hans-Joachim Barth ,  Jürgen Holz

IPC分类号： H01L21/20

CPC分类号： H01L23/5223 ,  H01L21/2885 ,  H01L21/76877 ,  H01L27/0805 ,  H01L28/75 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/162 ,  H05K3/107 ,  H01L2924/00

摘要： A method for fabricating an interconnect arrangement with increased capacitive coupling is described. A trench structure is formed in a first dielectric having a capacitor region with a first aspect ratio and an interconnect region with a second aspect ratio connected thereto. The trench structure of the interconnect region is completely filled by a first interconnect. The trench structure of the capacitor region is only partially filled by a first capacitor electrode and is completely filled by a capacitor dielectric and a second capacitor electrode. In a second dielectric formed thereon, a second interconnect with a contact via is formed, which is connected to the second capacitor electrode.

摘要翻译： 描述了一种用于制造具有增加的电容耦合的互连装置的方法。 在具有第一纵横比的电容器区域和与其连接的第二纵横比的互连区域的第一电介质中形成沟槽结构。 互连区域的沟槽结构由第一互连完全填充。 电容器区域的沟槽结构仅由第一电容器电极部分地填充，并且由电容器电介质和第二电容器电极完全填充。 在其上形成的第二电介质中，形成具有接触通孔的第二互连件，其连接到第二电容器电极。