利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

5 条记录 (耗时 0.012 秒)

    Method for a parallel production of an MOS transistor and a bipolar transistor
    3.
    发明授权
    Method for a parallel production of an MOS transistor and a bipolar transistor 失效
    并联生产MOS晶体管和双极晶体管的方法

    公开(公告)号：US07018884B2

    公开(公告)日：2006-03-28

    申请号：US10774349

    申请日：2004-02-06

    申请人： Adrian Berthold ,  Josef Böck ,  Jürgen Holz ,  Wolfgang Klein

    发明人： Adrian Berthold ,  Josef Böck ,  Jürgen Holz ,  Wolfgang Klein

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/8249

    摘要： The present invention provides a method for parallel production of an MOS transistor in an MOS area of a substrate and a bipolar transistor in a bipolar area of the substrate. The method comprises generating an MOS preparation structure in the MOS area, wherein the MOS preparation structure comprises an area provided for a channel, a gate dielectric, a gate electrode layer and a mask layer on the gate electrode layer. Further, a bipolar preparation structure is generated in the bipolar area, which comprises a conductive layer and a mask layer on the conductive layer. The mask layer is thinned in the area of the gate electrode. For determining a gate electrode and a base terminal area, common structuring of the gate electrode layer and the conductive layer is performed.

    摘要翻译： 本发明提供一种用于在基板的MOS区域和双极晶体管的基板的双极区域中并联制造MOS晶体管的方法。 该方法包括在MOS区域中产生MOS制备结构，其中MOS制备结构包括在栅极电极层上设置用于沟道的区域，栅极电介质，栅极电极层和掩模层。 此外，在双极性区域中产生双极制备结构，其在导电层上包括导电层和掩模层。 掩模层在栅电极的区域中变薄。 为了确定栅极电极和基极端子区域，执行栅电极层和导电层的共同构造。

    Method for a parallel production of an MOS transistor and a bipolar transistor
    4.
    发明授权
    Method for a parallel production of an MOS transistor and a bipolar transistor 失效
    并联生产MOS晶体管和双极晶体管的方法

    公开(公告)号：US07005337B2

    公开(公告)日：2006-02-28

    申请号：US10774338

    申请日：2004-02-06

    申请人： Adrian Berthold ,  Josef Boeck ,  Wolfgang Klein ,  Juergen Holz

    发明人： Adrian Berthold ,  Josef Boeck ,  Wolfgang Klein ,  Juergen Holz

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/8249

    摘要： The present invention provides a method for parallel production of an MOS transistor in an MOS area of a substrate and a bipolar transistor in a bipolar area of the substrate. The method includes generating an MOS preparation structure in the MOS area, wherein the MOS preparation structure includes an area provided for a channel, a gate dielectric, a gate electrode layer and a mask layer on the gate electrode layer. Further, a bipolar preparation structure is generated in the bipolar area, which includes a conductive layer and a mask layer on the conductive layer. For determining a gate electrode and a base terminal area, common structuring of the gate electrode layer and the conductive layer is performed. Further, the method includes simultaneous generation of isolating spacing layers on side walls of the gate electrode layer in the MOS area and the conductive layer in the bipolar area by depositing a first and second spacing layer. In the MOS area, the isolating spacing layers serve for defining areas to be doped and in the bipolar area for the isolation of a base area and an emitter area. Subsequently, selective etching of the first spacing layer and the second spacing layer is performed in the MOS area and the bipolar area.

    摘要翻译： 本发明提供一种用于在基板的MOS区域和双极晶体管的基板的双极区域中并联制造MOS晶体管的方法。 该方法包括在MOS区域中产生MOS制备结构，其中MOS制备结构包括在栅极电极层上设置用于沟道的区域，栅极电介质，栅极电极层和掩模层。 此外，在双极性区域中产生双极制备结构，该双极性区域在导电层上包括导电层和掩模层。 为了确定栅极电极和基极端子区域，执行栅电极层和导电层的共同构造。 此外，该方法包括通过沉积第一和第二间隔层在MOS区域中的栅电极层的侧壁和双极区域中的导电层同时产生隔离间隔层。 在MOS区域中，隔离间隔层用于限定待掺杂的区域和用于隔离基极区域和发射极区域的双极区域。 随后，在MOS区域和双极区域中执行第一间隔层和第二间隔层的选择性蚀刻。