公开(公告)号：US5253255A

公开(公告)日：1993-10-12

申请号：US612401

申请日：1990-11-02

申请人： Adrian Carbine

发明人： Adrian Carbine

IPC分类号： G06F11/267 ,  G01R31/28

CPC分类号： G06F11/2236

摘要： A VLSI chip debug and production test apparatus that allows an engineer to view the state of hundreds of signals internal to a chip in real-time without probing, which greatly simplifies the isolation of circuit, speed, logic, and microcode bugs. For production testing, it also provides the ability to check the state of these internal signals on a clock-by-clock basis. The mechanism uses a gated XOR-input serial shift-register cell (10), which is stepped out underneath major buses in otherwise unpopulated areas of the chip. Several of these cell groups are linked together to form a scanout path of the desired length, the operation of which is controlled with a single input pin (40). Output data is channeled through a shared output pin (19) to a VLSI tester (16). In the tester (16) the data (19) is checked and accumulated by back-end software over multiple test-loop iterations, and formatted into a readable form.

摘要翻译： 一种VLSI芯片调试和生产测试设备，允许工程师实时查看芯片内部数百个信号的状态，而无需探测，从而大大简化了电路，速度，逻辑和微码错误的隔离。 对于生产测试，它还提供了逐个时钟检查这些内部信号的状态的能力。 该机构使用门控XOR输入串行移位寄存器单元（10），该单元（10）在芯片的其他未填充区域内的主要总线下方走出。 这些单元组中的几个被连接在一起以形成所需长度的扫描输出路径，其操作由单个输入引脚（40）控制。 输出数据通过共享输出引脚（19）引导到VLSI测试仪（16）。 在测试器（16）中，数据（19）通过后端软件在多个测试循环迭代中进行检查和累加，并被格式化为可读形式。

公开(公告)号：US5222244A

公开(公告)日：1993-06-22

申请号：US630497

申请日：1990-12-20

申请人： Adrian Carbine ,  Frank S. Smith

发明人： Adrian Carbine ,  Frank S. Smith

IPC分类号： G06F9/28 ,  G06F9/30 ,  G06F9/318 ,  G06F9/35

CPC分类号： G06F9/30192 ,  G06F9/28 ,  G06F9/30145 ,  G06F9/35

摘要： An aliasing logic (100) in an instruction decoder. If a complex microinstruction flow is in progress, it operands can be accessed through alias registers (116). This allows indirect access to a source or destination register specified by the operands of the macrocode instruction or the opcode of the macroinstruction while executing a sequence of microinstructions. These aliased operands are maintained by the macroinstruction aliasing logic (100) in the register (116). The instruction decoder issues new instructions by driving a machine bus (110) with the correct information during each clock cycle. Mousetrap multiplexer (104) chooses between several sources of opcode and operand fields and routes the them to the machine bus (110) through several translation stages and multiplexers.

摘要翻译： 指令解码器中的混叠逻辑（100）。 如果复杂的微指令流程正在进行，则可以通过别名寄存器访问操作数（116）。 这允许在执行一个微指令序列时，间接访问由宏代码指令的操作数指定的源或目标寄存器或宏指令的操作码。 这些混叠的操作数由寄存器（116）中的宏指令混叠逻辑（100）保持。 指令解码器在每个时钟周期期间通过驱动具有正确信息的机器总线（110）来发出新的指令。 捕鼠器多路复用器（104）在操作码和操作数字段的几个来源之间进行选择，并通过多个翻译阶段和多路复用器将它们路由到机器总线（110）。

公开(公告)号：US06378061B1

公开(公告)日：2002-04-23

申请号：US08150784

申请日：1993-11-12

申请人： Adrian Carbine ,  Glenn J. Hinton ,  Frank S. Smith

发明人： Adrian Carbine ,  Glenn J. Hinton ,  Frank S. Smith

IPC分类号： G06F930

CPC分类号： G06F9/3808 ,  G06F9/30054 ,  G06F9/3017 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3857

摘要： An instruction decoder that issues new instructions by driving a machine bus (110) with the correct information during each clock cycle. This information is either extracted from the current instruction to be executed, or is recycled from the previous contents (106) of the machine bus when a scoreboarding operation has been performed. Mousetrap multiplexer (104) chooses between several sources of opcode and operand fields and routes them to the machine bus (110) through several translation stages and multiplexers. The decision of which source to use is based on what kind of instruction is currently being looked at by the instruction queue in the instruction fetch unit. The instruction queue notifies the instruction decoder that the next instruction is to be either a RISC operation (including register, memory, and/or branch instructions) or an instruction which is part of a microcode flow. If a complex macroinstruction flow is in progress, its operands can be accessed through alias registers. This allows indirect access to a source or destination register specified by the operands of the macrocode instruction or the opcode of the macroinstruction while executing a sequence of microinstructions. These aliased operands are maintained by the macroinstruction aliasing logic (100).

摘要翻译： 一种指令解码器，其通过在每个时钟周期期间以正确的信息驱动机器总线（110）来发布新的指令。 当执行记分操作时，该信息是从当前要执行的指令中提取的，或者从机器总线的先前内容（106）中循环回收的。 捕鼠器多路复用器（104）在操作码和操作数字段的几个来源之间进行选择，并通过多个转换级和多路复用器将它们路由到机器总线（110）。 使用哪个源的决定是基于指令提取单元中的指令队列当前正在查看什么样的指令。 指令队列通知指令解码器下一条指令是RISC操作（包括寄存器，存储器和/或分支指令）或作为微代码流的一部分的指令。 如果复杂的宏指令流正在进行，则可以通过别名寄存器访问其操作数。 这允许在执行一个微指令序列时，间接访问由宏代码指令的操作数指定的源或目标寄存器或宏指令的操作码。 这些混叠的操作数由宏指令混叠逻辑（100）维护。

公开(公告)号：US6055656A

公开(公告)日：2000-04-25

申请号：US434163

申请日：1995-05-02

申请人： James A. Wilson, Jr. ,  Anthony C. Miller ,  Michael W. Rhodehamel ,  Adrian Carbine ,  Derek B. I. Feltham ,  Sumeet Agrawal

发明人： James A. Wilson, Jr. ,  Anthony C. Miller ,  Michael W. Rhodehamel ,  Adrian Carbine ,  Derek B. I. Feltham ,  Sumeet Agrawal

IPC分类号： G01R31/3185 ,  G06F11/267 ,  G01R31/28

CPC分类号： G06F11/2236 ,  G01R31/318572

摘要： A scheme for accessing a control register bus and control registers of a microprocessor through a test access port which is configured to an established testing standard. A test access port (TAP) of a microprocessor is configured to communicate serially based on a technique specified in the IEEE 1149.1 standard. External serial instructions are converted for parallel transfer to provide control signals for accessing the internal structures. Serial address and data signals are also converted for parallel transfer to access internal structures on a control register bus and parallel outputs are converted to serial format for external output. By permitting external access to low level internal bus architecture, system testing and debug can be performed by utilizing external programming.

摘要翻译： 用于通过配置成建立的测试标准的测试访问端口访问控制寄存器总线和微处理器的控制寄存器的方案。 微处理器的测试访问端口（TAP）被配置为基于IEEE 1149.1标准中规定的技术来串行地进行通信。 外部串行指令被转换为并行传输，以提供用于访问内部结构的控制信号。 串行地址和数据信号也被转换为并行传输以访问控制寄存器总线上的内部结构，并行输出转换为用于外部输出的串行格式。 通过允许外部访问低级内部总线架构，可以通过利用外部编程来执行系统测试和调试。