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公开(公告)号：US5850368A
公开(公告)日：1998-12-15
申请号：US922194
申请日：1997-09-02
CPC分类号： G11C8/04
摘要： A counter comprised of two flip flops and a multiplexer produces a sequential or interleaved address sequence. The addresses produced are used to access memory elements in a Burst Extended Data Output Dynamic Random Access Memory (Burst EDO or BEDO DRAM). Input addresses in combination with a sequence select signal are logically combined to produce a multiplexer select input which selects between true and compliment outputs of a first flip flop to couple to an input of a second flip flop to specify a toggle condition for the second flip flop. Outputs of the counter are compared with outputs of an input address latch to detect the end of a burst sequence and initialize the device for another burst access. A transition of the Read/Write control line during a burst access will terminate the burst access and initialize the device for another burst access.
摘要翻译： 由两个触发器和多路复用器组成的计数器产生顺序或交错地址序列。 所产生的地址用于访问突发扩展数据输出动态随机存取存储器（Burst EDO或BEDO DRAM）中的存储器元件。 与序列选择信号组合的输入地址被逻辑地组合以产生多路复用器选择输入，其选择第一触发器的真实和补码输出以耦合到第二触发器的输入以指定第二触发器的切换条件 。 将计数器的输出与输入地址锁存器的输出进行比较，以检测突发序列的结束，并初始化用于另一个突发存取的设备。 在脉冲串访问期间读/写控制线的转换将终止脉冲串访问并初始化设备以进行另一个突发存取。
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公开(公告)号：US5802010A
公开(公告)日：1998-09-01
申请号：US661478
申请日：1996-06-10
IPC分类号： G06F12/06 , G11C7/10 , G11C11/407 , G11C8/00
CPC分类号： G11C7/109 , G06F12/0638 , G11C11/407 , G11C7/1018 , G11C7/1021 , G11C7/1024 , G11C7/1039 , G11C7/1045 , G11C7/1078 , G11C7/1096 , G06F2212/2022
摘要： An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and initialize the device for another burst access. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and other memory circuit designs.
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公开(公告)号：US5526320A
公开(公告)日：1996-06-11
申请号：US370761
申请日：1994-12-23
IPC分类号： G06F12/06 , G11C7/10 , G11C11/407 , G11C8/00
CPC分类号： G11C7/109 , G06F12/0638 , G11C11/407 , G11C7/1018 , G11C7/1021 , G11C7/1024 , G11C7/1039 , G11C7/1045 , G11C7/1078 , G11C7/1096 , G06F2212/2022
摘要： An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and initialize the device for another burst access. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and other memory circuit designs.
摘要翻译： 集成电路存储器件被设计用于高速数据访问和与现有存储器系统的兼容性。 地址选通信号用于锁存第一个地址。 在突发访问周期期间，地址在设备内部增加，并具有额外的地址选通转换。 只有在每次突发访问开始时才需要新的内存地址。 读/写命令每次突发存取发出一次，无需在器件周期频率下切换读/写控制线。 突发访问期间读/写控制线的转换将终止突发访问，重置突发长度计数器并初始化设备以进行另一个突发访问。 该器件与现有的扩展数据输出DRAM器件引脚排列，快速页面模式和扩展数据输出单列直插存储器模块引脚排列以及其他存储器电路设计兼容。
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公开(公告)号：US5838620A
公开(公告)日：1998-11-17
申请号：US796148
申请日：1997-02-06
申请人： Paul S. Zagar , Adrian E. Ong
发明人： Paul S. Zagar , Adrian E. Ong
CPC分类号： G11C29/785 , G11C29/838
摘要： In an integrated circuit having addressable primary elements and redundant elements which can be programmed to replace primary elements, a circuit and method are provided for cancelling and replacing redundant elements. A circuit is described which can be used in a memory such as a dynamic random access memory (DRAM) which uses a selectively blowable anti-fuse to disable a redundant element which was previously programmed to replace a defective primary element. The disclosure describes a method for permanently cancelling the defective redundant element and replacing the defective redundant element with another redundant element.
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5.发明授权Dynamic random access memory having decoding circuitry for partial memory blocks 失效具有用于部分存储器块的解码电路的动态随机存取存储器
公开(公告)号：US5901105A
公开(公告)日：1999-05-04
申请号：US869035
申请日：1997-06-05
申请人： Adrian E Ong , Paul S. Zagar , Troy Manning , Brent Keeth , Ken Waller
发明人： Adrian E Ong , Paul S. Zagar , Troy Manning , Brent Keeth , Ken Waller
CPC分类号： G11C29/785 , G11C11/4096 , G11C29/80 , G11C29/88 , G11C5/025 , G11C7/10 , G11C29/36
摘要： A semiconductor dynamic random-access memory (DRAM) device embodying numerous features that collectively and/or individually prove beneficial and advantageous with regard to such considerations as density, power consumption, speed, and redundancy is disclosed. The device is a 64 Mbit DRAM comprising eight substantially identical 8 Mbit partial array blocks (PABs), each pair of PABs comprising a 16 Mbit quadrant of the device. Between the top two quadrants and between the bottom two quadrants are column blocks containing I/O read/write circuitry, column redundancy fuses, and column decode circuitry. Column select lines originate from the column blocks and extend right and left across the width of each quadrant. Each PAB comprises eight substantially identical 1 Mbit sub-array blocks (SABs). Associated with each SAB are a plurality of local row decoder circuits functioning to receive partially decoded row addresses from a column predecoder circuit and generating local row addresses supplied to the SAB with which they are associated. Various pre- and/or post-packaging options are provided for enabling a large degree of versatility, redundancy, and economy of design. Programmable options of the disclosed device are programmable by means of both laser fuses and electrical fuses. In the RAS chain, circuitry is provided for simulating the RC time constant behavior of word lines and digit lines during memory accesses, such that memory access cycle time can be optimized. Test data compression circuitry optimizes the process of testing each cell in the array. On-chip topology circuitry simplifies the testing of the device.
摘要翻译： 公开了一种体现许多特征的半导体动态随机存取存储器（DRAM）装置，它们集中和/或单独地证明了在诸如密度，功耗，速度和冗余度之类的考虑方面是有利和有利的。 该器件是包括八个基本上相同的8兆位部分阵列块（PAB）的64Mbit DRAM，每对PAB包括该器件的16Mb象限。 顶部两个象限之间和底部两个象限之间是包含I / O读/写电路，列冗余保险丝和列解码电路的列块。 列选择线来自列块，并在每个象限的宽度上左右延伸。 每个PAB包括八个基本上相同的1兆位子阵列块（SAB）。 与每个SAB相关联的是多个本地行解码器电路，用于从列预解码器电路接收部分解码的行地址，并产生提供给与它们相关联的SAB的本地行地址。 提供了各种前置和/或后封装选项，以实现大量多功能性，冗余性和设计经济性。 所公开的设备的可编程选项可通过激光熔丝和电熔丝两者来编程。 在RAS链中，提供电路用于在存储器访问期间模拟字线和数字线的RC时间常数行为，使得可以优化存储器访问周期时间。 测试数据压缩电路优化了测试阵列中每个单元的过程。 片上拓扑电路简化了器件的测试。
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6.发明授权
公开(公告)号：US5761145A
公开(公告)日：1998-06-02
申请号：US685783
申请日：1996-07-24
申请人： Paul S. Zagar , Brent Keeth , Adrian E. Ong
发明人： Paul S. Zagar , Brent Keeth , Adrian E. Ong
IPC分类号： G06F12/16 , G01R31/30 , G06F11/22 , G11C29/00 , G11C29/02 , G11C29/04 , G11C29/44 , G11C29/50 , G11C13/00
CPC分类号： G11C29/70 , G01R31/3004 , G06F11/22 , G11C29/02 , G11C29/44 , G11C29/50 , G11C29/83 , G11C29/832 , G11C29/88 , G11C11/401 , G11C2029/5006
摘要： An integrated circuit memory device has multiple subarray partitions which can be independently isolated from the remaining circuitry on the integrated circuit. Subarrays of the integrated circuit can be independently tested. Should a subarray of the integrated circuit be found inoperable it is electrically isolated from the remaining circuitry on the integrated circuit so that it cannot interfere with the normal operation of the remaining circuitry. Defects such as power to ground shorts in a subarray which would have previously been catastrophic can be electrically isolated allowing the remaining functional subarrays to be utilized. Integrated circuit repair by isolation of inoperative elements eliminates the current draw and other performance degradations that have previously been associated with integrated circuits with defects repaired through the incorporation of redundant elements alone.
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7.发明授权Efficient method for obtaining usable parts from a partially good memory integrated circuit 有权从部分良好的存储器集成电路获得可用部件的高效方法
公开(公告)号：US6097647A
公开(公告)日：2000-08-01
申请号：US382526
申请日：1999-08-25
申请人： Paul S. Zagar , Brent Keeth , Adrian E. Ong
发明人： Paul S. Zagar , Brent Keeth , Adrian E. Ong
IPC分类号： G06F12/16 , G01R31/30 , G06F11/22 , G11C29/00 , G11C29/02 , G11C29/04 , G11C29/44 , G11C29/50 , G11C7/00
CPC分类号： G11C29/70 , G01R31/3004 , G06F11/22 , G11C29/02 , G11C29/44 , G11C29/50 , G11C29/83 , G11C29/832 , G11C29/88 , G11C11/401 , G11C2029/5006
摘要： An integrated circuit memory device has multiple subarray partitions which can be independently isolated from the remaining circuitry on the integrated circuit. Subarrays of the integrated circuit can be independently tested. Should a subarray of the integrated circuit be found inoperable it is electrically isolated from the remaining circuitry on the integrated circuit so that it cannot interfere with the normal operation of the remaining circuitry. Defects such as power to ground shorts in a subarray which would have previously been catastrophic can be electrically isolated allowing the remaining functional subarrays to be utilized. Integrated circuit repair by isolation of inoperative elements eliminates the current draw and other performance degradations that have previously been associated with integrated circuits with defects repaired through the incorporation of redundant elements alone.
摘要翻译： 集成电路存储器件具有多个子阵列分隔，其可以独立地与集成电路上的剩余电路隔离。 集成电路的子阵列可以独立测试。 如果发现集成电路的子阵列不可操作，则它与集成电路上的剩余电路电隔离，使得其不能干扰剩余电路的正常操作。 以前曾经是灾难性的子阵列中的诸如地面短路的电力的缺陷可以电隔离，允许利用剩余的功能子阵列。 通过隔离不起作用元件的集成电路修复消除了以前与集成电路相关的电流消耗和其他性能下降，缺陷通过单独使用冗余元件进行维修。
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公开(公告)号：US5912579A
公开(公告)日：1999-06-15
申请号：US133586
申请日：1998-08-13
申请人： Paul S. Zagar , Adrian E. Ong
发明人： Paul S. Zagar , Adrian E. Ong
CPC分类号： G11C29/785 , G11C29/838
摘要： In an integrated circuit having addressable primary elements and redundant elements which can be programmed to replace primary elements, a circuit and method are provided for cancelling and replacing redundant elements. A circuit is described which can be used in a memory such as a dynamic random access memory (DRAM) which uses a selectively blowable anti-fuse to disable a redundant element which was previously programmed to replace a defective primary element. The disclosure describes a method for permanently cancelling the defective redundant element and replacing the defective redundant element with another redundant element.
摘要翻译： 在具有可寻址主要元件的集成电路和可编程为替代主要元件的冗余元件中，提供了用于取消和替换冗余元件的电路和方法。 描述了可以用于存储器中的电路，例如动态随机存取存储器（DRAM），其使用可选择地可吹出的反熔丝来禁用先前被编程为替换有缺陷的主要元件的冗余元件。 本公开描述了一种用于永久地消除有缺陷的冗余元件并用另一个冗余元件替换有缺陷的冗余元件的方法。
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公开(公告)号：US5677884A
公开(公告)日：1997-10-14
申请号：US816203
申请日：1997-02-28
申请人： Paul S. Zagar , Adrian E. Ong
发明人： Paul S. Zagar , Adrian E. Ong
CPC分类号： G11C29/785 , G11C29/838
摘要： In an integrated circuit having addressable primary elements and redundant elements which can be programmed to replace primary elements, a circuit and method are provided for cancelling and replacing redundant elements. A circuit is described which can be used in a memory such as a dynamic random access memory (DRAM) which uses a selectively blowable anti-fuse to disable a redundant element which was previously programmed to replace a defective primary element. The disclosure describes a method for permanently cancelling the defective redundant element and replacing the defective redundant element with another redundant element.
摘要翻译： 在具有可寻址主要元件的集成电路和可编程为替代主要元件的冗余元件中，提供了用于取消和替换冗余元件的电路和方法。 描述了可以用于存储器中的电路，例如动态随机存取存储器（DRAM），其使用可选择地可吹出的反熔丝来禁用先前被编程为替换有缺陷的主要元件的冗余元件。 本公开描述了一种用于永久地消除有缺陷的冗余元件并用另一个冗余元件替换有缺陷的冗余元件的方法。
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公开(公告)号：US06208568B1
公开(公告)日：2001-03-27
申请号：US09133714
申请日：1998-08-13
申请人： Paul S. Zagar , Adrian E. Ong
发明人： Paul S. Zagar , Adrian E. Ong
IPC分类号： G11C1300
CPC分类号： G11C29/785 , G11C29/838
摘要： In an integrated circuit having addressable primary elements and redundant elements which can be programmed to replace primary elements, a circuit and method are provided for cancelling and replacing redundant elements. A circuit is described which can be used in a memory such as a dynamic random access memory (DRAM) which uses a selectively blowable anti-fuse to disable a redundant element which was previously programmed to replace a defective primary element. The disclosure describes a method for permanently cancelling the defective redundant element and replacing the defective redundant element with another redundant element.
摘要翻译： 在具有可寻址主要元件的集成电路和可编程为替代主要元件的冗余元件中，提供了用于取消和替换冗余元件的电路和方法。 描述了可以用于存储器中的电路，例如动态随机存取存储器（DRAM），其使用可选择地可吹出的反熔丝来禁用先前被编程为替换有缺陷的主要元件的冗余元件。 本公开描述了一种用于永久地消除有缺陷的冗余元件并用另一个冗余元件替换有缺陷的冗余元件的方法。
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