公开(公告)号：US5850368A

公开(公告)日：1998-12-15

申请号：US922194

申请日：1997-09-02

申请人： Adrian E. Ong ,  Paul S. Zagar ,  Brett L. Williams ,  Troy A. Manning

发明人： Adrian E. Ong ,  Paul S. Zagar ,  Brett L. Williams ,  Troy A. Manning

IPC分类号： G11C8/04 ,  G11C8/00

CPC分类号： G11C8/04

摘要： A counter comprised of two flip flops and a multiplexer produces a sequential or interleaved address sequence. The addresses produced are used to access memory elements in a Burst Extended Data Output Dynamic Random Access Memory (Burst EDO or BEDO DRAM). Input addresses in combination with a sequence select signal are logically combined to produce a multiplexer select input which selects between true and compliment outputs of a first flip flop to couple to an input of a second flip flop to specify a toggle condition for the second flip flop. Outputs of the counter are compared with outputs of an input address latch to detect the end of a burst sequence and initialize the device for another burst access. A transition of the Read/Write control line during a burst access will terminate the burst access and initialize the device for another burst access.

摘要翻译： 由两个触发器和多路复用器组成的计数器产生顺序或交错地址序列。 所产生的地址用于访问突发扩展数据输出动态随机存取存储器（Burst EDO或BEDO DRAM）中的存储器元件。 与序列选择信号组合的输入地址被逻辑地组合以产生多路复用器选择输入，其选择第一触发器的真实和补码输出以耦合到第二触发器的输入以指定第二触发器的切换条件 。 将计数器的输出与输入地址锁存器的输出进行比较，以检测突发序列的结束，并初始化用于另一个突发存取的设备。 在脉冲串访问期间读/写控制线的转换将终止脉冲串访问并初始化设备以进行另一个突发存取。

公开(公告)号：US5802010A

公开(公告)日：1998-09-01

申请号：US661478

申请日：1996-06-10

申请人： Paul S. Zagar ,  Brett L. Williams ,  Troy A. Manning

发明人： Paul S. Zagar ,  Brett L. Williams ,  Troy A. Manning

IPC分类号： G06F12/06 ,  G11C7/10 ,  G11C11/407 ,  G11C8/00

CPC分类号： G11C7/109 ,  G06F12/0638 ,  G11C11/407 ,  G11C7/1018 ,  G11C7/1021 ,  G11C7/1024 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1096 ,  G06F2212/2022

摘要： An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and initialize the device for another burst access. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and other memory circuit designs.

公开(公告)号：US5526320A

公开(公告)日：1996-06-11

申请号：US370761

申请日：1994-12-23

申请人： Paul S. Zagar ,  Brett L. Williams ,  Troy A. Manning

发明人： Paul S. Zagar ,  Brett L. Williams ,  Troy A. Manning

IPC分类号： G06F12/06 ,  G11C7/10 ,  G11C11/407 ,  G11C8/00

CPC分类号： G11C7/109 ,  G06F12/0638 ,  G11C11/407 ,  G11C7/1018 ,  G11C7/1021 ,  G11C7/1024 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1096 ,  G06F2212/2022

摘要： An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and initialize the device for another burst access. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and other memory circuit designs.

摘要翻译： 集成电路存储器件被设计用于高速数据访问和与现有存储器系统的兼容性。 地址选通信号用于锁存第一个地址。 在突发访问周期期间，地址在设备内部增加，并具有额外的地址选通转换。 只有在每次突发访问开始时才需要新的内存地址。 读/写命令每次突发存取发出一次，无需在器件周期频率下切换读/写控制线。 突发访问期间读/写控制线的转换将终止突发访问，重置突发长度计数器并初始化设备以进行另一个突发访问。 该器件与现有的扩展数据输出DRAM器件引脚排列，快速页面模式和扩展数据输出单列直插存储器模块引脚排列以及其他存储器电路设计兼容。

公开(公告)号：US5675549A

公开(公告)日：1997-10-07

申请号：US457651

申请日：1995-06-01

申请人： Adrian Ong ,  Paul S. Zagar ,  Brett L. Wiliams ,  Troy A. Manning

发明人： Adrian Ong ,  Paul S. Zagar ,  Brett L. Wiliams ,  Troy A. Manning

IPC分类号： G06F12/06 ,  G11C7/10 ,  G11C11/407 ,  G11C8/00

CPC分类号： G06F12/0638 ,  G11C11/407 ,  G11C7/1018 ,  G11C7/1021 ,  G11C7/1024 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/1096 ,  G06F2212/2022

摘要： A counter comprised of two flip flops and a multiplexer produces a sequential or interleaved address sequence. The addresses produced are used to access memory elements in a Burst Extended Data Output Dynamic Random Access Memory (Burst EDO or BEDO DRAM). Input addresses in combination with a sequence select signal are logically combined to produce a multiplexer select input which selects between true and compliment outputs of a first flip flop to couple to an input of a second flip flop to specify a toggle condition for the second flip flop. Outputs of the counter are compared with outputs of an input address latch to detect the end of a burst sequence and initialize the device for another burst access. A transition of the Read/Write control line during a burst access will terminate the burst access and initialize the device for another burst access.

摘要翻译： 由两个触发器和多路复用器组成的计数器产生顺序或交错地址序列。 所产生的地址用于访问突发扩展数据输出动态随机存取存储器（Burst EDO或BEDO DRAM）中的存储器元件。 与序列选择信号组合的输入地址被逻辑地组合以产生多路复用器选择输入，其选择第一触发器的真实和补码输出以耦合到第二触发器的输入以指定第二触发器的切换条件 。 将计数器的输出与输入地址锁存器的输出进行比较，以检测突发序列的结束，并初始化用于另一个突发存取的设备。 在脉冲串访问期间读/写控制线的转换将终止脉冲串访问并初始化设备以进行另一个突发存取。

公开(公告)号：US5812488A

公开(公告)日：1998-09-22

申请号：US811696

申请日：1997-03-05

申请人： Paul S. Zagar ,  Troy A. Manning ,  Todd Merritt

发明人： Paul S. Zagar ,  Troy A. Manning ,  Todd Merritt

IPC分类号： G06F12/06 ,  G11C7/10 ,  G11C11/407 ,  G11C8/00

CPC分类号： G11C7/109 ,  G06F12/0638 ,  G11C11/407 ,  G11C7/1018 ,  G11C7/1021 ,  G11C7/1024 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1096 ,  G06F2212/2022

摘要： An integrated circuit memory device is described which can operate at high data speeds. The memory device can either store or retrieve data from the memory in a burst access operation. The burst operations latches a memory address from external address lines and internally generates additional memory addresses. A clock signal is provided to synchronize the burst operations. The clock signal is independent of an address latch signal used to latch an external address.

摘要翻译： 描述了可以在高数据速度下操作的集成电路存储器件。 存储器设备可以在突发存取操作中存储或从存储器检索数据。 突发操作从外部地址线锁存存储器地址，并在内部生成额外的存储器地址。 提供时钟信号以同步突发操作。 时钟信号与用于锁存外部地址的地址锁存信号无关。

公开(公告)号：US5668773A

公开(公告)日：1997-09-16

申请号：US552199

申请日：1995-11-02

申请人： Paul S. Zagar ,  Troy A. Manning ,  Todd Merritt

发明人： Paul S. Zagar ,  Troy A. Manning ,  Todd Merritt

IPC分类号： G06F12/06 ,  G11C7/10 ,  G11C11/407 ,  G11C8/00

CPC分类号： G11C7/109 ,  G06F12/0638 ,  G11C11/407 ,  G11C7/1018 ,  G11C7/1021 ,  G11C7/1024 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1096 ,  G06F2212/2022

摘要： An integrated circuit memory device is described which can operate at high data speeds. The memory device can either store or retrieve data from the memory in a burst access operation. The burst operations latches a memory address from external address lines and internally generates additioned memory addresses. A clock signed is provided to synchronize the burst operations. The clock signed is independent of an address latch signal used to latch an external address.

摘要翻译： 描述了可以以高数据速度操作的集成电路存储器件。 存储器设备可以在突发存取操作中存储或从存储器检索数据。 突发操作从外部地址线锁存存储器地址，并在内部生成加法存储器地址。 提供了一个签名的时钟以使突发操作同步。 所签的时钟独立于用于锁存外部地址的地址锁存信号。

公开(公告)号：US20130342375A1

公开(公告)日：2013-12-26

申请号：US13531090

申请日：2012-06-22

申请人： Troy A. Manning ,  Troy D. Larsen ,  Martin L. Culley ,  Jeffrey L. Meader ,  Steve G. Bard ,  Dean C. Eyres

发明人： Troy A. Manning ,  Troy D. Larsen ,  Martin L. Culley ,  Jeffrey L. Meader ,  Steve G. Bard ,  Dean C. Eyres

IPC分类号： H03M7/30

CPC分类号： G06F3/0608 ,  G06F3/0661 ,  G06F3/0673 ,  H03M7/30 ,  H03M7/60 ,  H03M7/6082

摘要： The present disclosure includes apparatuses and methods for data compression and management. A number of methods include receiving a number of data segments corresponding to a managed unit amount of data, determining a respective compressibility of each of the number of data segments, compressing each of the number of data segments in accordance with its respective determined compressibility, forming a compressed managed unit that includes compressed and/or uncompressed data segments corresponding to the number of data segments corresponding to the managed unit amount of data, and forming a page of data that comprises at least the compressed managed unit.

摘要翻译： 本公开包括用于数据压缩和管理的装置和方法。 多种方法包括接收对应于被管理单元数据量的多个数据段，确定多个数据段中的每一个的相应可压缩性，根据其各自确定的压缩性来压缩数据段中的每一个，形成 压缩的被管理单元，其包括对应于与被管理单元数据量对应的数据段的数量的压缩和/或未压缩数据段，以及形成至少包括压缩的被管理单元的数据页。

公开(公告)号：US20120226887A1

公开(公告)日：2012-09-06

申请号：US13041402

申请日：2011-03-06

申请人： Martin L. Culley ,  Troy A. Manning ,  Troy D. Larsen

发明人： Martin L. Culley ,  Troy A. Manning ,  Troy D. Larsen

IPC分类号： G06F12/10 ,  G06F12/14

CPC分类号： G06F3/0665 ,  G06F12/00 ,  G06F12/0246 ,  G06F12/0292 ,  G06F12/04 ,  G06F12/10 ,  G06F12/1027 ,  G06F12/1408 ,  G06F12/1475 ,  G06F2212/7201 ,  G06F2212/7202 ,  Y02D10/13

摘要： The present disclosure includes methods for logical address translation, methods for operating memory systems, and memory systems. One such method includes receiving a command associated with a LA, wherein the LA is in a particular range of LAs and translating the LA to a physical location in memory using an offset corresponding to a number of physical locations skipped when writing data associated with a range of LAs other than the particular range.

摘要翻译： 本公开包括用于逻辑地址转换的方法，用于操作存储器系统的方法和存储器系统。 一种这样的方法包括接收与LA相关联的命令，其中LA在LAs的特定范围内，并且使用对应于当写入与范围相关联的数据时跳过的物理位置的数量来将LA转换到存储器中的物理位置 的特定范围以外的。

公开(公告)号：US20110267917A1

公开(公告)日：2011-11-03

申请号：US13184168

申请日：2011-07-15

申请人： Troy A. Manning

发明人： Troy A. Manning

IPC分类号： G11C8/10 ,  G11C8/00

CPC分类号： G11C8/10 ,  G11C11/4087

摘要： Electronic apparatus, systems, and methods may operate structures to access a portion of a row of a memory array without accessing the entire row. Additional apparatus, systems, and methods are disclosed.

摘要翻译： 电子设备，系统和方法可以操作结构以访问存储器阵列的行的一部分而不访问整个行。 公开了附加装置，系统和方法。

公开(公告)号：US07954031B2

公开(公告)日：2011-05-31

申请号：US12649137

申请日：2009-12-29

申请人： Troy A. Manning

发明人： Troy A. Manning

IPC分类号： G01R31/28

CPC分类号： G11C29/022 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/20 ,  G11C11/4096 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

摘要： Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated from the captured first group. A second group of applied data signals is then captured and determined to have been properly captured when the second group corresponds to the group of expect data signals. In this way, when a captured series of data signals is shifted in time from an expected capture point, subsequent captured data signals are compared to their correct expected data signals in order to determine whether that group, although shifted in time, was nonetheless correctly captured. A pattern generator generates expect data signals in this manner, and may be utilized in a variety of integrated circuits, such as an SLDRAM.

摘要翻译： 为具有已知序列的一系列应用数据信号产生预期数据信号，以确定数据信号组是否被适当地捕获。 捕获应用数据信号的第一组，并从捕获的第一组生成一组期望数据信号。 然后当第二组对应于期望数据信号组时，捕获并确定第二组应用数据信号以被适当地捕获。 以这种方式，当捕获的一系列数据信号从期望的捕获点在时间上移动时，将后续捕获的数据信号与其正确的预期数据信号进行比较，以便确定该组虽然在时间上移动仍然被正确捕获 。 模式发生器以这种方式生成期望数据信号，并且可以用于各种集成电路中，例如SLDRAM。