公开(公告)号：US09443561B1

公开(公告)日：2016-09-13

申请号：US14719200

申请日：2015-05-21

Applicant: Advanced Micro Devices, Inc.

Inventor： David Roberts ,  Yasuko Eckert ,  Mitesh Meswani ,  Indrani Paul

IPC: G11C5/02 ,  H04L12/933 ,  G06F13/42 ,  G11C5/06 ,  G06F13/40

CPC classification number: G11C5/02 ,  G06F13/4027 ,  G06F13/4068 ,  G06F13/42 ,  G11C5/025 ,  G11C5/06 ,  G11C5/063 ,  Y02D10/14 ,  Y02D10/151

Abstract: Embodiments are described for a communications interconnect scheme for 3D stacked memory devices. A ring network design is used for networks of memory chips organized as individual devices with multiple dies or wafers. The design comprises a three-tier ring network where each ring serves a different set of memory blocks. One ring or set of rings interconnects memory within a die (inter-bank), a second ring or set of rings interconnects memory across die in a stack (inter-die), and the third ring or set of rings interconnects memory across stacks or chip packages (inter-stack).

Abstract translation: 针对3D堆叠存储器件的通信互连方案描述了实施例。 环形网络设计用于组织为具有多个管芯或晶片的单独器件的存储器芯片的网络。 该设计包括三层环网，其中每个环服务不同的存储块集合。 一个环或一组环将管芯内的存储器互相互连（第二环或一组环）在堆叠（管芯间）中跨芯片互连存储器，并且第三环或一组环将堆叠互连存储器 芯片封装（堆叠）。