公开(公告)号：US11144473B2

公开(公告)日：2021-10-12

申请号：US16007027

申请日：2018-06-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Arkaprava Basu ,  Michael LeBeane ,  Eric Van Tassell

IPC: G06F12/1036 ,  G06F12/1009 ,  G06F9/50 ,  G06F9/48 ,  G06F13/16 ,  G06F13/22

Abstract: A data processing system includes a memory, a group of input/output (I/O) devices, an input/output memory management unit (IOMMU). The IOMMU is connected to the memory and adapted to allocate a hardware resource from among a group of hardware resources to receive an address translation request for a memory access from an I/O device. The IOMMU detects address translation requests from the plurality of I/O devices. The IOMMU reorders the address translation requests such that an order of dispatching an address translation request is based on a policy associated with the I/O device that is requesting the memory access. The IOMMU selectively allocates a hardware resource to the input/output device, based on the policy that is associated with the I/O device in response to the reordering.

公开(公告)号：US20190384722A1

公开(公告)日：2019-12-19

申请号：US16007027

申请日：2018-06-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Arkaprava Basu ,  Michael LeBeane ,  Eric Van Tassell

IPC: G06F12/1036 ,  G06F12/1009 ,  G06F9/50 ,  G06F9/48 ,  G06F13/16 ,  G06F13/22

Abstract: A data processing system includes a memory, a group of input/output (I/O) devices, an input/output memory management unit (IOMMU). The IOMMU is connected to the memory and adapted to allocate a hardware resource from among a group of hardware resources to receive an address translation request for a memory access from an I/O device. The IOMMU detects address translation requests from the plurality of I/O devices. The IOMMU reorders the address translation requests such that an order of dispatching an address translation request is based on a policy associated with the I/O device that is requesting the memory access. The IOMMU selectively allocates a hardware resource to the input/output device, based on the policy that is associated with the I/O device in response to the reordering.

公开(公告)号：US10437736B2

公开(公告)日：2019-10-08

申请号：US15852442

申请日：2017-12-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Arkaprava Basu ,  Eric Van Tassell ,  Mark Oskin ,  Guilherme Cox ,  Gabriel Loh

IPC: G06F12/00 ,  G06F12/1009 ,  G06F12/1027 ,  G06F9/38 ,  G06F13/40 ,  G06F9/48 ,  G06F13/42

Abstract: A data processing system includes a memory and an input output memory management unit that is connected to the memory. The input output memory management unit is adapted to receive batches of address translation requests. The input output memory management unit has instructions that identify, from among the batches of address translation requests, a later batch having a lower number of memory access requests than an earlier batch, and selectively schedules access to a page table walker for each address translation request of a batch.

公开(公告)号：US20190196978A1

公开(公告)日：2019-06-27

申请号：US15852442

申请日：2017-12-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Arkaprava Basu ,  Eric Van Tassell ,  Mark Oskin ,  Guilherme Cox ,  Gabriel Loh

IPC: G06F12/1009 ,  G06F12/1027 ,  G06F9/38 ,  G06F13/40 ,  G06F13/42 ,  G06F9/48

CPC classification number: G06F12/1009 ,  G06F9/3887 ,  G06F9/4843 ,  G06F12/1027 ,  G06F13/4022 ,  G06F13/4282 ,  G06F2212/65 ,  G06F2212/68 ,  G06F2213/0026

Abstract: A data processing system includes a memory and an input output memory management unit that is connected to the memory. The input output memory management unit is adapted to receive batches of address translation requests. The input output memory management unit has instructions that identify, from among the batches of address translation requests, a later batch having a lower number of memory access requests than an earlier batch, and selectively schedules access to a page table walker for each address translation request of a batch.