公开(公告)号：US10541013B1

公开(公告)日：2020-01-21

申请号：US16189185

申请日：2018-11-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell J. Schreiber ,  Tawfik Ahmed ,  Ilango Jeyasubramanian

IPC: G11C8/18 ,  G11C8/08 ,  G11C11/408 ,  G11C11/418

Abstract: A word line driver circuit receives a word line input signal and supplies a word line driver output signal to a worldline. The word line driver circuit includes a transistor having a first current carrying terminal coupled to the word line driver output signal and a second current carrying terminal coupled to a first node. A gate of the transistor is coupled to the word line input signal, and the transistor provides a path from the word line to the first node while the word line is asserted. A programmable word line underdrive circuit is coupled between the first node and a ground node to reduce a voltage on the word line output signal. A plurality of word line driver circuits are coupled to the first node and use the word line underdrive circuit to underdrive their respective word lines.

公开(公告)号：US12009025B2

公开(公告)日：2024-06-11

申请号：US17358527

申请日：2021-06-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Tawfik Ahmed ,  Andrew J. Robison ,  Russell J. Schreiber

IPC: G11C11/419 ,  G11C11/412 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C11/412 ,  G11C11/418

Abstract: A method for accessing a memory cell includes enabling precharging of a bit line of the memory cell before a next access of the memory cell. The method includes disabling the precharging after a first interval if the next access is a write. The method includes disabling the precharging after a second interval if the next access is a read. The first interval is shorter than the second interval.

公开(公告)号：US20220415386A1

公开(公告)日：2022-12-29

申请号：US17358527

申请日：2021-06-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Tawfik Ahmed ,  Andrew J. Robison ,  Russell J. Schreiber

IPC: G11C11/419 ,  G11C11/418 ,  G11C11/412

Abstract: A method for accessing a memory cell includes enabling precharging of a bit line of the memory cell before a next access of the memory cell. The method includes disabling the precharging after a first interval if the next access is a write. The method includes disabling the precharging after a second interval if the next access is a read. The first interval is shorter than the second interval.

公开(公告)号：US20190180799A1

公开(公告)日：2019-06-13

申请号：US15838955

申请日：2017-12-12

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Tawfik Ahmed

IPC: G11C7/12 ,  G06F1/32 ,  G11C11/4074 ,  G11C7/10 ,  G11C7/22

CPC classification number: G11C7/12 ,  G06F1/3275 ,  G06F1/3296 ,  G11C7/1096 ,  G11C7/22 ,  G11C11/4074

Abstract: A memory device includes a memory cell coupled to a bitline and a bitline complement. A first capacitive structure is charged with a first voltage source such as a memory supply voltage. A second capacitive structure is charged with a second voltage source such as a core supply voltage. A coupling structure selectively and capacitively couples the first capacitive structure and the second capacitive structure to the bitline or the bitline complement, thereby applying a negative bitline write assist to the memory cell during a write operation.

公开(公告)号：US10438636B2

公开(公告)日：2019-10-08

申请号：US15834644

申请日：2017-12-07

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Tawfik Ahmed ,  Amlan Ghosh ,  Keith A. Kasprak ,  Ricardo Cantu

IPC: G11C7/12 ,  H01L23/522 ,  G11C7/10 ,  G11C5/06

Abstract: Write assist circuitry facilitates increased voltage applied to a memory device such as a memory cell or bitcell in changing a logical state of the memory device during a write operation. The write assist circuitry includes a second capacitive line or “metal cap” in addition to a first capacitive line coupled to one of a pair of bitlines to which voltage may be selectively applied. The capacitive lines provide increased write assistance to the memory device. The second capacitive line structurally lies in a second orientation and is formed in an integrated circuit second metal layer relative to the first capacitive line in some embodiments. The additional capacitive line provides negative bitline assistance by selectively driving its corresponding bitlines to be negative during a write operation.

公开(公告)号：US10332570B1

公开(公告)日：2019-06-25

申请号：US15838955

申请日：2017-12-12

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Tawfik Ahmed

IPC: G11C7/12 ,  G06F1/3234 ,  G11C7/22 ,  G11C11/4074 ,  G11C7/10 ,  G06F1/3296

Abstract: A memory device includes a memory cell coupled to a bitline and a bitline complement. A first capacitive structure is charged with a first voltage source such as a memory supply voltage. A second capacitive structure is charged with a second voltage source such as a core supply voltage. A coupling structure selectively and capacitively couples the first capacitive structure and the second capacitive structure to the bitline or the bitline complement, thereby applying a negative bitline write assist to the memory cell during a write operation.