公开(公告)号：US20150121046A1

公开(公告)日：2015-04-30

申请号：US14523730

申请日：2014-10-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Thomas Kunjan ,  Scott T. Bingham ,  Marius Evers ,  James D. Williams

IPC: G06F9/30 ,  G06F12/08

CPC classification number: G06F9/30043 ,  G06F9/3834 ,  G06F9/3855 ,  G06F9/3857 ,  G06F12/0875 ,  G06F12/1027 ,  G06F2212/452 ,  G06F2212/684

Abstract: The present invention provides a method and apparatus for supporting embodiments of an out-of-order load to load queue structure. One embodiment of the apparatus includes a load queue for storing memory operations adapted to be executed out-of-order with respect to other memory operations. The apparatus also includes a load order queue for cacheable operations that ordered for a particular address.

Abstract translation: 本发明提供了一种用于支持负载队列结构的无序负载的实施例的方法和装置。 该装置的一个实施例包括用于存储适于相对于其他存储器操作无序执行的存储器操作的加载队列。 该装置还包括针对特定地址排序的可缓存操作的加载顺序队列。

公开(公告)号：US09916243B2

公开(公告)日：2018-03-13

申请号：US14522137

申请日：2014-10-23

Applicant: Advanced Micro Devices, Inc.

Inventor： William L. Walker ,  Paul J. Moyer ,  Richard M. Born ,  Eric Morton ,  David Christie ,  Marius Evers ,  Scott T. Bingham

IPC: G06F12/08 ,  G06F9/46 ,  G06F12/0808 ,  G06F12/1045 ,  G06F12/1027 ,  G06F9/52 ,  G06F13/38 ,  G06F12/10

CPC classification number: G06F12/0808 ,  G06F9/467 ,  G06F9/526 ,  G06F12/1027 ,  G06F12/1054 ,  G06F2209/522 ,  G06F2212/621 ,  G06F2212/682 ,  G06F2212/683

Abstract: A method and apparatus for performing a bus lock and a translation lookaside buffer invalidate transaction includes receiving, by a lock master, a lock request from a first processor in a system. The lock master sends a quiesce request to all processors in the system, and upon receipt of the quiesce request from the lock master, all processors cease issuing any new transactions and issue a quiesce granted transaction. Upon receipt of the quiesce granted transactions from all processors, the lock master issues a lock granted message that includes an identifier of the first processor. The first processor performs an atomic transaction sequence and sends a first lock release message to the lock master upon completion of the atomic transaction sequence. The lock master sends a second lock release message to all processors upon receiving the first lock release message from the first processor.

公开(公告)号：US20150120976A1

公开(公告)日：2015-04-30

申请号：US14522137

申请日：2014-10-23

Applicant: Advanced Micro Devices, Inc.

Inventor： William L. Walker ,  Paul J. Moyer ,  Richard M. Born ,  Eric Morton ,  David Christie ,  Marius Evers ,  Scott T. Bingham

IPC: G06F12/08 ,  G06F9/46 ,  G06F12/10

CPC classification number: G06F12/0808 ,  G06F9/467 ,  G06F9/526 ,  G06F12/1027 ,  G06F12/1054 ,  G06F2209/522 ,  G06F2212/621 ,  G06F2212/682 ,  G06F2212/683

Abstract: A method and apparatus for performing a bus lock and a translation lookaside buffer invalidate transaction includes receiving, by a lock master, a lock request from a first processor in a system. The lock master sends a quiesce request to all processors in the system, and upon receipt of the quiesce request from the lock master, all processors cease issuing any new transactions and issue a quiesce granted transaction. Upon receipt of the quiesce granted transactions from all processors, the lock master issues a lock granted message that includes an identifier of the first processor. The first processor performs an atomic transaction sequence and sends a first lock release message to the lock master upon completion of the atomic transaction sequence. The lock master sends a second lock release message to all processors upon receiving the first lock release message from the first processor.

Abstract translation: 用于执行总线锁定和翻译后备缓冲器无效事务的方法和装置包括由锁定主机接收来自系统中的第一处理器的锁定请求。 锁定主机向系统中的所有处理器发送静默请求，并且在收到来自锁定主机的停顿请求后，所有处理器都停止发出任何新的事务并发出静默授权交易。 在从所有处理器接收到暂停许可的交易之后，锁定主机发出包含第一处理器的标识符的锁授予消息。 第一个处理器执行原子事务序列，并在原子事务序列完成时向锁主机发送第一个锁定释放消息。 当从第一处理器接收到第一锁定释放消息时，锁定主机向所有处理器发送第二锁定释放消息。