公开(公告)号：US20220100504A1

公开(公告)日：2022-03-31

申请号：US17032301

申请日：2020-09-25

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Benjamin TSIEN ,  Alexander J. BRANOVER ,  John PETRY ,  Chen-Ping YANG ,  Rostyslav KYRYCHYNSKYI ,  Vydhyanathan KALYANASUNDHARAM

IPC: G06F9/30 ,  G06F9/4401 ,  G06F9/38 ,  G06F9/46 ,  G06F13/40

Abstract: A processing system that includes a shared data fabric resets a first client processor while operating a second client processor. The first client processor is instructed to stop making requests to one or more devices of the shared data fabric. Status communications are blocked between the first client processor and a memory controller, the second client processor, or both, such that the first client processor enters a temporary offline state. The first client processor is indicated as being non-coherent. Accordingly, when the processor is reset some errors and efficiency losses due messages sent during or prior to the reset are prevented.

公开(公告)号：US20250085848A1

公开(公告)日：2025-03-13

申请号：US18888463

申请日：2024-09-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Vydhyanathan KALYANASUNDHARAM

IPC: G06F3/06

Abstract: Systems, methods, and techniques are provided for a fabric addressable memory. A memory access request is received from a host computing device attached via one edge port of one or more interconnect switches, the memory access request directed to a destination segment of a physical fabric memory block that is allocated in local physical memory of the host computing device. The edge port accesses a stored mapping between segments of the physical fabric memory block and one or more destination port identifiers that are each associated with a respective edge port of the fabric addressable memory. The memory access request is routed by the one edge port to a destination edge port based on the stored mapping.

公开(公告)号：US20230112007A1

公开(公告)日：2023-04-13

申请号：US17957469

申请日：2022-09-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Vydhyanathan KALYANASUNDHARAM

IPC: G06F3/06

Abstract: Systems, methods, and techniques are provided for a fabric addressable memory. A memory access request is received from a host computing device attached via one edge port of one or more interconnect switches, the memory access request directed to a destination segment of a physical fabric memory block that is allocated in local physical memory of the host computing device. The edge port accesses a stored mapping between segments of the physical fabric memory block and one or more destination port identifiers that are each associated with a respective edge port of the fabric addressable memory. The memory access request is routed by the one edge port to a destination edge port based on the stored mapping.

公开(公告)号：US20250098181A1

公开(公告)日：2025-03-20

申请号：US18829848

申请日：2024-09-10

Applicant: Advanced Micro Devices, Inc.

Inventor： Alan D. SMITH ,  Samuel NAFFZIGER ,  Joe MACRI ,  James R. MAGRO ,  Vydhyanathan KALYANASUNDHARAM

IPC: H10B80/00 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18

Abstract: A package device includes a processing device, memory dies and a memory controller. The memory controller die is coupled to the processing device and the memory dies. The memory controller die controls communication from the processing device to the memory dies and to an external memory device. The external memory device is external to the memory dies.

公开(公告)号：US20230205523A1

公开(公告)日：2023-06-29

申请号：US17562853

申请日：2021-12-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Vydhyanathan KALYANASUNDHARAM ,  Joseph L. GREATHOUSE ,  Shyam SEKAR

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/48 ,  G06F13/42

CPC classification number: G06F9/3004 ,  G06F9/3001 ,  G06F9/325 ,  G06F9/485 ,  G06F13/4221

Abstract: A system includes a hardware compare and swap (CAS) module communicatively coupled to a bus, the CAS module to perform an atomic operation in response to a first request from a first request agent for the atomic operation to be performed on a data value that is shared among a plurality of request agents and obtain a first result value. The atomic operation includes initiating a CAS command via the bus. The CAS module performs the atomic operation in response to a second request from a second request agent and obtains a second result value. Responsive to determining a failure to successfully process one or more of the first request or the second request, the hardware CAS module repetitively performs the atomic operation, for one or more of the first request or the second request.