公开(公告)号：US20180061767A1

公开(公告)日：2018-03-01

申请号：US15692947

申请日：2017-08-31

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yuan-Feng CHIANG ,  Cong-Wei CHEN ,  I-Ting CHI ,  Shao-An CHEN

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/29 ,  H01L21/56 ,  H01L21/48 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L23/295 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/065 ,  H01L2224/19 ,  H01L2224/214 ,  H01L2224/96

Abstract: A semiconductor package structure includes a semiconductor substrate, at least one semiconductor die, an encapsulant, a protection layer, a plurality of conductive elements and a redistribution layer. The semiconductor die is disposed on the semiconductor substrate. The encapsulant covers at least a portion of the semiconductor die, and has a first surface and a lateral surface. The protection layer covers the first surface and the lateral surface of the encapsulant. The conductive elements surround the lateral surface of the encapsulant. The redistribution layer electrically connects the semiconductor die and the conductive elements.

公开(公告)号：US20220352066A1

公开(公告)日：2022-11-03

申请号：US17243456

申请日：2021-04-28

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Shao-An CHEN ,  Chih-Yi HUANG ,  Ping Cing SHEN

IPC: H01L23/522 ,  H01L23/31 ,  H01L23/00 ,  H01L21/66 ,  H01L21/48

Abstract: An electronic device package includes an encapsulated electronic component, a redistribution layer (RDL) and a conductive via. The RDL is disposed above the encapsulated electronic component. The RDL includes a circuit layer comprising a conductive pad including a pad portion having a curved edge and a center of curvature, and an extension portion protruding from the pad portion and having a curved edge and a center of curvature. The circuit layer further includes a dielectric layer above the RDL. The conductive via is disposed in the dielectric layer and connected to the conductive pad of the RDL. A center of the conductive via is closer to the center of curvature of the edge of the extension portion than to the center of curvature of the edge of the pad portion.

公开(公告)号：US20180047651A1

公开(公告)日：2018-02-15

申请号：US15675610

申请日：2017-08-11

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Shao-An CHEN ,  Po-Wei LU ,  Ming Tsung SHEN ,  Yu-Tzu PENG

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/538 ,  H01L21/56

Abstract: The present disclosure relates to wafer level packages including one or more semiconductor dies and a method of manufacturing the same. A method comprises: providing a carrier having a predetermined area, disposing a semiconductor device on the predetermined area, and forming a sacrificial wall on a periphery of the predetermined area.