公开(公告)号：US20170330870A1

公开(公告)日：2017-11-16

申请号：US15453656

申请日：2017-03-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu CHEN ,  Kuang-Hsiung CHEN ,  Sheng-Ming WANG ,  Yu-Ying LEE ,  Yu-Tzu PENG

IPC: H01L25/10 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L21/4853 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/13 ,  H01L24/24 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0217 ,  H01L2224/02175 ,  H01L2224/0218 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/05564 ,  H01L2224/05582 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/13147 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24105 ,  H01L2224/24146 ,  H01L2224/24246 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H05K1/144 ,  H05K3/284 ,  H05K2203/1316

Abstract: A semiconductor package comprises a substrate, a pad, a first isolation layer, an interconnection layer, and a conductive post. The substrate has a first surface and a second surface opposite the first surface. The pad has a first portion and a second portion on the first surface of the substrate. The first isolation layer is disposed on the first surface and covers the first portion of the pad, and the first isolation layer has a top surface. The interconnection layer is disposed on the second portion of the pad and has a top surface. The conductive post is disposed on the top surface of the first isolation layer and on the top surface of the interconnection layer. The top surface of the first isolation layer and the top surface of the interconnection layer are substantially coplanar.

公开(公告)号：US20180350626A1

公开(公告)日：2018-12-06

申请号：US16102527

申请日：2018-08-13

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu CHEN ,  Kuang-Hsiung CHEN ,  Sheng-Ming WANG ,  Yu-Ying LEE ,  Yu-Tzu PENG

IPC: H01L21/48 ,  H01L25/10 ,  H01L23/00

Abstract: A semiconductor package includes: (1) a substrate; (2) a first isolation layer disposed on the substrate, the first isolation layer including an opening; (3) a pad disposed on the substrate and exposed from the opening; (4) an interconnection layer disposed on the pad; and (5) a conductive post including a bottom surface, the bottom surface having a first part disposed on the interconnection layer and a plurality of second parts disposed on the first isolation layer.

公开(公告)号：US20180233457A1

公开(公告)日：2018-08-16

申请号：US15430355

申请日：2017-02-10

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu CHEN ,  Kuang-Hsiung CHEN ,  Sheng-Ming WANG ,  I-Cheng WANG ,  Wun-Jheng SYU ,  Yu-Tzu PENG

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/367 ,  H01L23/29 ,  H01L25/065 ,  H01L23/538 ,  H01L21/56 ,  H01L21/768 ,  H01L21/683 ,  H01L25/00 ,  H01L25/10

CPC classification number: H01L23/552 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76885 ,  H01L21/76895 ,  H01L23/295 ,  H01L23/3107 ,  H01L23/3675 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2224/18 ,  H01L2224/32145 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2225/1058 ,  H01L2225/1094

Abstract: A semiconductor device package includes a first circuit layer having a first surface and a second surface opposite the first side, a first electronic component, a shielding element, a shielding layer and a molding layer. The first electronic component is disposed over the first surface of the first circuit layer, and electrically connected to the first circuit layer. The shielding element is disposed over the first surface of the first circuit layer, and is electrically connected to the first circuit layer. The shielding element is disposed adjacent to at least one side of the first electronic component. The shielding layer is disposed over the first electronic component and the shielding element, and the shielding layer is electrically connected to the shielding element. The molding layer encapsulates the first electronic component, the shielding element and a portion of the shielding layer.

公开(公告)号：US20180047651A1

公开(公告)日：2018-02-15

申请号：US15675610

申请日：2017-08-11

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Shao-An CHEN ,  Po-Wei LU ,  Ming Tsung SHEN ,  Yu-Tzu PENG

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/538 ,  H01L21/56

Abstract: The present disclosure relates to wafer level packages including one or more semiconductor dies and a method of manufacturing the same. A method comprises: providing a carrier having a predetermined area, disposing a semiconductor device on the predetermined area, and forming a sacrificial wall on a periphery of the predetermined area.