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    Method of forming a resistor and integrated circuitry having a resistor construction
    2.
    发明授权
    Method of forming a resistor and integrated circuitry having a resistor construction 有权
    形成电阻器的方法和具有电阻器结构的集成电路

    公开(公告)号：US06130137A

    公开(公告)日：2000-10-10

    申请号：US170792

    申请日：1998-10-13

    申请人： Kirk Prall ,  Pierre C. Fazan ,  Aftab Ahmad ,  Howard E. Rhodes ,  Werner Juengling ,  Pai-Hung Pan ,  Tyler Lowrey

    发明人： Kirk Prall ,  Pierre C. Fazan ,  Aftab Ahmad ,  Howard E. Rhodes ,  Werner Juengling ,  Pai-Hung Pan ,  Tyler Lowrey

    IPC分类号： H01L21/02 ,  H01L21/20

    CPC分类号： H01L28/20

    摘要： A method of forming a resistor from semiconductive material includes, a) providing a substrate; b) providing a layer of semiconductive material over the substrate; c) providing a pair of openings into the semiconductive material layer; d) plugging the pair of openings with an electrically conductive material to define a pair of electrically conductive pillars within the semiconductive material, the pair of pillars having semiconductive material extending therebetween to provide a resistor construction; and e) providing a conductive node to each of the electrically conductive pillars. An integrated circuit incorporating a resistor construction includes, i) a layer of semiconductive material; ii) a pair of electrically conductive pillars provided within the semiconductive material layer, the pair of pillars being separated from one another and thereby having a mass of the semiconductive material extending therebetween; and iii) an electrically conductive node in electrical connection with each of the respective conductive pillars. Alternately, a resistor is provided within a semiconductive substrate using different concentration diffusion regions.

    摘要翻译： 从半导体材料形成电阻器的方法包括：a）提供衬底; b）在衬底上提供半导体材料层; c）在半导体材料层中提供一对开口; d）用导电材料堵塞所述一对开口，以在所述半导体材料内限定一对导电柱，所述一对支柱具有在其间延伸的半导体材料以提供电阻器结构; 以及e）为每个导电柱提供导电节点。 结合电阻器结构的集成电路包括：i）半导体材料层; ii）设置在半导体材料层内的一对导电柱，所述一对柱彼此分离，从而具有在其间延伸的半导体材料的质量; 以及iii）与每个相应的导电柱电连接的导电节点。 或者，使用不同的浓度扩散区域在半导体衬底内提供电阻器。

    Method of forming a resistor and integrated circuitry having a resistor construction
    6.
    发明授权
    Method of forming a resistor and integrated circuitry having a resistor construction 失效
    形成电阻器的方法和具有电阻器结构的集成电路

    公开(公告)号：US5668037A

    公开(公告)日：1997-09-16

    申请号：US679705

    申请日：1996-07-11

    申请人： Kirk Prall ,  Pierre C. Fazan ,  Aftab Ahmad ,  Howard E. Rhodes ,  Werner Juengling ,  Pai-Hung Pan ,  Tyler Lowrey

    发明人： Kirk Prall ,  Pierre C. Fazan ,  Aftab Ahmad ,  Howard E. Rhodes ,  Werner Juengling ,  Pai-Hung Pan ,  Tyler Lowrey

    IPC分类号： H01L21/02 ,  H01L27/06 ,  H01L27/08 ,  H01L21/70

    CPC分类号： H01L28/20 ,  H01L27/0629 ,  H01L27/0802 ,  Y10S148/136

    摘要： A method of forming a resistor from semiconductive material includes, a) providing a substrate; b) providing a layer of semiconductive material over the substrate; c) providing a pair of openings into the semiconductive material layer; d) plugging the pair of openings with an electrically conductive material to define a pair of electrically conductive pillars within the semiconductive material, the pair of pillars having semiconductive material extending therebetween to provide a resistor construction; and e) providing a conductive node to each of the electrically conductive pillars. An integrated circuit incorporating a resistor construction includes, i) a layer of semiconductive material; ii) a pair of electrically conductive pillars provided within the semiconductive material layer, the pair of pillars being separated from one another and thereby having a mass of the semiconductive material extending therebetween; and iii) an electrically conductive node in electrical connection with each of the respective conductive pillars. Alternately, a resistor is provided within a semiconductive substrate using different concentration diffusion regions.

    摘要翻译： 从半导体材料形成电阻器的方法包括：a）提供衬底; b）在衬底上提供半导体材料层; c）在半导体材料层中提供一对开口; d）用导电材料堵塞所述一对开口，以在所述半导体材料内限定一对导电柱，所述一对支柱具有在其间延伸的半导体材料以提供电阻器结构; 以及e）为每个导电柱提供导电节点。 结合电阻器结构的集成电路包括：i）半导体材料层; ii）设置在半导体材料层内的一对导电柱，所述一对柱彼此分离，从而具有在其间延伸的半导体材料的质量; 以及iii）与每个相应的导电柱电连接的导电节点。 或者，使用不同的浓度扩散区域在半导体衬底内提供电阻器。

    High performance PMOSFET using split-polysilicon CMOS process incorporating advanced stacked capacitior cells for fabricating multi-megabit DRAMS
    7.
    发明授权
    High performance PMOSFET using split-polysilicon CMOS process incorporating advanced stacked capacitior cells for fabricating multi-megabit DRAMS 失效
    采用分裂多晶硅CMOS工艺的高性能PMOSFET，包含用于制造多兆位DRAMS的先进的堆叠电容单元

    公开(公告)号：US5716862A

    公开(公告)日：1998-02-10

    申请号：US491179

    申请日：1995-06-16

    申请人： Aftab Ahmad ,  Randhir P. S. Thakur ,  Kirk Prall ,  Tyler Lowrey ,  Brett Rolfson

    发明人： Aftab Ahmad ,  Randhir P. S. Thakur ,  Kirk Prall ,  Tyler Lowrey ,  Brett Rolfson

    IPC分类号： H01L21/28 ,  H01L21/265 ,  H01L21/02 ,  H01L21/70 ,  H01L27/00

    CPC分类号： H01L21/28061 ,  H01L21/28247

    摘要： This invention is a process for manufacturing dynamic random access memories using stacked container capacitor cells in a split-polysilicon CMOS manufacturing flow. The split-polysilicon flow denotes that N-channel and P-channel transistor gates are formed from a single conductive layer (typically a doped polysilicon layer) using separate masking steps. In one embodiment of the present invention teaches a semiconductor manufacturing process for forming p-channel devices by the steps of: defining p-channel transistor gate electrodes having substantially vertical sidewalls over n-well regions; performing a p-type impurity implant into the n-well regions to form p-channel source and drain terminals on opposing sides of each the p-channel transistor gate electrodes; performing an angled n-type impurity implant into the n-well regions to form an n-type halo around the p-channel source and drain terminals; performing a low temperature oxidation step at a temperature ranging between 600.degree.-957.degree. C., to form poly gate sidewall oxidation about the vertical sidewalls of the p-channel transistor gate electrodes; and performing a p-type impurity implant into the n-well regions.

    摘要翻译： 本发明是使用分裂多晶硅CMOS制造流程中的堆叠容器电容器单元制造动态随机存取存储器的方法。 分离多晶硅流程表示使用单独的掩蔽步骤由单个导电层（通常为掺杂多晶硅层）形成N沟道和P沟道晶体管栅极。 在本发明的一个实施例中，教导了通过以下步骤形成p沟道器件的半导体制造工艺：定义在n-阱区上具有基本上垂直的侧壁的p沟道晶体管栅电极; 对n阱区域进行p型杂质注入，以在每个p沟道晶体管栅电极的相对侧上形成p沟道源极和漏极端子; 在n阱区域中执行倾斜的n型杂质注入以在p沟道源极和漏极端子周围形成n型光晕; 在600〜957℃的温度范围内进行低温氧化步骤，以形成围绕p沟道晶体管栅极垂直侧壁的多晶硅侧壁氧化; 以及对n阱区进行p型杂质注入。

    Method of forming CMOS devices using independent thickness spacers in a split-polysilicon DRAM process
    8.
    发明授权
    Method of forming CMOS devices using independent thickness spacers in a split-polysilicon DRAM process 失效
    在分裂多晶硅DRAM工艺中使用独立厚度间隔物形成CMOS器件的方法

    公开(公告)号：US5489546A

    公开(公告)日：1996-02-06

    申请号：US449300

    申请日：1995-05-24

    申请人： Aftab Ahmad ,  Pierre C. Fazan ,  Charles H. Dennison

    发明人： Aftab Ahmad ,  Pierre C. Fazan ,  Charles H. Dennison

    IPC分类号： H01L21/8238 ,  H01L21/8242

    CPC分类号： H01L21/823864

    摘要： NMOS and PMOS devices are formed in a split-polysilicon CMOS process using independent thickness transistor gate spacers, and using a silicon nitride layer as a mask for the p-channel region during an n+ source/drain implant step of the n-channel region. The p-channel spacer is formed significantly thicker than the n-channel spacer, thereby reducing lateral diffusion of p-type dopant species under the p-channel gate and avoiding short channel effects to improve device reliability and performance. P-channel transistor junction depth and lateral diffusion is further reduced by performing an n-channel arsenic source/drain implant before the p-channel source/drain boron difluoride implant, although the p-channel transistor gate is etched before the n-channel gate. Moreover, since the p-channel transistor gate is etched before the n-channel gate, the p-channel gate sidewalls are reoxidized as well as the n-channel gate sidewalls for improved gate oxide integrity.

    摘要翻译： 使用独立厚度的晶体管栅极隔离器，在分离多晶硅CMOS工艺中形成NMOS和PMOS器件，并且在n沟道区域的n +源极/漏极注入步骤期间使用氮化硅层作为p沟道区的掩模。 p沟道间隔物形成为比n沟道间隔物显着更厚，从而减少p型掺杂剂物质在p沟道栅极下的横向扩散，并且避免短沟道效应以提高器件的可靠性和性能。 尽管p沟道晶体管栅极在n沟道栅极之前被蚀刻，但是在p沟道源极/漏极二硼化硼注入之前执行n沟道砷源极/漏极注入来进一步减小P沟道晶体管结深度和横向扩散。 。 此外，由于在n沟道栅极之前蚀刻p沟道晶体管栅极，所以p沟道栅极侧壁以及n沟道栅极侧壁被再氧化以改善栅极氧化物的完整性。

    Method of fabricating an enhanced dynamic random access memory (DRAM) cell capacitor using multiple polysilicon texturization
    9.
    发明授权
    Method of fabricating an enhanced dynamic random access memory (DRAM) cell capacitor using multiple polysilicon texturization 失效
    使用多个多晶硅纹理化制造增强型动态随机存取存储器（DRAM）单元电容器的方法

    公开(公告)号：US5208176A

    公开(公告)日：1993-05-04

    申请号：US603528

    申请日：1990-10-25

    申请人： Aftab Ahmad ,  Pierre C. Fazan ,  Ruojia Lee

    发明人： Aftab Ahmad ,  Pierre C. Fazan ,  Ruojia Lee

    IPC分类号： H01L21/308 ,  H01L21/32 ,  H01L21/334

    CPC分类号： H01L29/66181 ,  H01L21/3081 ,  H01L21/32 ,  Y10S438/964

    摘要： A DRAM cell having a doped monocrystalline silicon substrate for the cell's lower capacitor plate whose surface has been texturized multiple times to enhance cell capacitance. After texturization, a thin silicon nitride layer is deposited on top of the texturized substrate, followed by the deposition of a poly layer, which functions as the cell's upper, or field, capacitor plate. The nitride layer, conformal and thin compared to the surface texture of the mono substrate, transfers the texture of the substrate to the cell plate layer. The effective capacitor plate area is substantially augmented, resulting in a cell capacitance increase of at least approximately fifty percent compared to a conventional planar cell utilizing identical wafer area. The substrate is texturized by texturizing a thin polycrystalline silicon (poly) starter layer that has been deposited on top of the substrate by using an anisotropic etch or wet oxidation step, and then allowing the poly starter layer to be consumed, transferring the texture created on the poly starter layer to the underlying substrate. By subjecting the starter layer to either an etch or an oxidation step, atoms at the grain boundaries of the starter layer react more rapidly, thus establishing the texturization pattern. Once established, the starter layer's texturization pattern is transferred to the monocrystalline silicon surface by either etching or oxidizing the starter layer. Performing this texturization process multiple times produces greater texturization due to the consumption of the successive poly starter layers along their respective, uniquely superimposed grain boundaries.

    摘要翻译： 具有用于电池的下电容器板的掺杂单晶硅衬底的DRAM单元，其表面已被多次构造以增强单元电容。 在纹理化之后，将薄的氮化硅层沉积在纹理化衬底的顶部上，随后沉积多层，其用作电池的上部或场域电容器板。 与单基板的表面纹理相比，保形和薄的氮化物层将基板的纹理转移到单元板层。 与使用相同晶片面积的常规平面单元相比，有效电容器板面积基本上增加，导致电池电容增加至少约百分之五十。 通过使用各向异性蚀刻或湿氧化步骤，已经沉积在衬底的顶部上的薄多晶硅（多晶）起始层进行纹理化，然后允许多晶硅起始层被消耗，转移在 多晶硅起始层到底层基板。 通过使起始层进行蚀刻或氧化步骤，起始层的晶界处的原子反应更快，从而建立了纹理化模式。 一旦建立，起始层的纹理化图案通过蚀刻或氧化起始层被转移到单晶硅表面。 由于沿着它们各自的独特叠加的晶界而消耗连续的多晶硅起始层，多次进行这种纹理化过程会产生更大的纹理化。

    Semiconductor processing method of fabricating field effect transistors
    10.
    发明授权
    Semiconductor processing method of fabricating field effect transistors 失效
    制造场效应晶体管的半导体处理方法

    公开(公告)号：US06326250B1

    公开(公告)日：2001-12-04

    申请号：US08990200

    申请日：1997-12-22

    申请人： Aftab Ahmad ,  Kirk Prall

    发明人： Aftab Ahmad ,  Kirk Prall

    IPC分类号： H01L21336

    CPC分类号： H01L29/6653 ,  H01L21/823814

    摘要： In one aspect of the invention, a semiconductor processing method includes: a) providing a semiconductor substrate; b) defining a first conductivity type region and a second conductivity type region of the semiconductor substrate; c) providing a first transistor gate over the first type region which defines a first source area and a first drain area operatively adjacent thereto; d) providing a second transistor gate over the second type region which defines a second source area and a second drain area operatively adjacent thereto; and e) blanket implanting a conductivity enhancing dopant of the second conductivity type through the first source and drain areas of the first conductivity region and the second source and drain areas of the second conductivity region to provide second conductivity type regular LDD implant regions within the substrate operatively adjacent the first transistor gate and to provide second conductivity type halo implant regions within the substrate operatively adjacent the second transistor gate. In another aspect, a semiconductor processing method includes: a) providing a semiconductor substrate; b) providing a transistor gate over the semiconductor substrate; c) providing spacers adjacent the transistor gate; d) providing electrically conductive source and drain implant regions within the substrate operatively adjacent the transistor gate; e) implanting a conductivity enhancing dopant into the previously formed electrically conductive source and drain regions; and f) driving the conductivity enhancing dopant under the spacers to form graded junction regions.

    摘要翻译： 在本发明的一个方面，半导体处理方法包括：a）提供半导体衬底; b）限定半导体衬底的第一导电类型区域和第二导电类型区域; c）在所述第一类型区域上提供限定与其可操作地相邻的第一源区域和第一漏极区域的第一晶体管栅极; d）在所述第二类型区域上提供限定与其可操作地相邻的第二源极区域和第二漏极区域的第二晶体管栅极; 以及e）通过所述第一导电区域的所述第一源极和漏极区域以及所述第二导电区域的所述第二源极和漏极区域覆盖所述第二导电类型的电导率增强掺杂剂，以在所述衬底内提供第二导电类型的常规LDD注入区域 可操作地与第一晶体管栅极相邻并且在衬底内提供可操作地邻近第二晶体管栅极的第二导电类型的晕圈注入区域。 另一方面，半导体处理方法包括：a）提供半导体衬底; b）在半导体衬底上提供晶体管栅极; c）提供与晶体管栅极相邻的间隔物; d）在所述衬底内提供与所述晶体管栅极可操作地相邻的导电源极和漏极注入区域; e）将电导率增强掺杂剂注入到先前形成的导电源极和漏极区域中; 以及f）在所述间隔物下驱动所述导电性增强掺杂剂以形成渐变连接区域。