公开(公告)号：US20190084826A1

公开(公告)日：2019-03-21

申请号：US16088021

申请日：2017-03-23

Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH

Inventor： Navab SINGH ,  Daw Don CHEAM

IPC: B81B7/00 ,  B81C1/00

Abstract: A Through Silicon Interposer Wafer and Method of Manufacturing the Same A through silicon interposer wafer having at least one cavity formed therein for MEMS applications and a method of manufacturing the same are provided. The through silicon interposer wafer includes one or more filled silicon vias formed sufficiently proximate to the at least one cavity to provide support for walls of the at least one cavity during subsequent processing of the interposer wafer.

公开(公告)号：US20180312399A1

公开(公告)日：2018-11-01

申请号：US15768531

申请日：2016-10-06

Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH

Inventor： Navab SINGH ,  Jae Wung LEE ,  Srinivas MERUGU

IPC: B81C1/00 ,  B81B7/00 ,  B06B1/06

CPC classification number: B81C1/00246 ,  B06B1/0666 ,  B81B7/008 ,  B81B2201/0271 ,  B81B2203/0127 ,  B81B2203/0307 ,  B81B2203/0315 ,  B81B2203/04 ,  B81B2207/015 ,  B81B2207/07 ,  B81C1/00039 ,  B81C2203/0735

Abstract: Various embodiments may provide a device arrangement. The device arrangement may include a substrate including a conductive layer. The device arrangement may further include a microelectromechanical systems (MEMS) device monolithically integrated with the substrate, wherein the MEMS device may be electrically coupled to the conductive layer. A cavity may be defined through the conductive layer for acoustically isolating the MEMS device MEMS device from the substrate. At least one anchor structure may be defined by the conductive layer to support the MEMS device.

公开(公告)号：US20130200327A1

公开(公告)日：2013-08-08

申请号：US13745993

申请日：2013-01-21

Applicant: Agency for Science, Technology and Research

Inventor： Xinpeng WANG ,  Xiang LI ,  Navab SINGH ,  Guo-Qiang Patrick LO

IPC: H01L45/00

CPC classification number: H01L45/04 ,  B82Y10/00 ,  B82Y40/00 ,  H01L27/2409 ,  H01L27/2454 ,  H01L45/1226 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16 ,  Y10S977/762 ,  Y10S977/943

Abstract: According to embodiments of the present invention, a resistive memory arrangement is provided. The resistive memory arrangement includes a nanowire, and a resistive memory cell including a resistive layer including a resistive changing material, wherein at least a section of the resistive layer is arranged covering at least a portion of a surface of the nanowire, and a conductive layer arranged on at least a part of the resistive layer. According to further embodiments of the present invention, a method of forming a resistive memory arrangement is also provided.

Abstract translation: 根据本发明的实施例，提供了一种电阻式存储装置。 电阻性存储器装置包括纳米线和包括电阻层的电阻性存储单元，该电阻层包括电阻变化材料，其中电阻层的至少一部分布置成覆盖纳米线表面的至少一部分，导电层 布置在电阻层的至少一部分上。 根据本发明的另外的实施例，还提供了形成电阻式存储装置的方法。