公开(公告)号：US20150311920A1

公开(公告)日：2015-10-29

申请号：US14691732

申请日：2015-04-21

Applicant: Agency for Science, Technology and Research

Inventor： Xueqiang Wang

IPC: H03M13/15 ,  H03M13/00 ,  G06F11/10

CPC classification number: H03M13/1545 ,  G06F11/1012 ,  H03M13/152 ,  H03M13/1525 ,  H03M13/6502 ,  H03M13/6575

Abstract: According to embodiments of the present invention, a decoder for a memory device is provided. The decoder includes an error detection circuitry configured to multiply a vector of one or more data words with a parity matrix to determine a plurality of syndrome values and generate a plurality of coefficients from multiplying a syndrome vector with an inverse of a syndrome matrix; and an error correction circuitry configured to perform a Chien search on a first part of the plurality of coefficients to determine error indicators indicating error locations in a first part of the one or more data words, and subsequently on a second part of the plurality of coefficients to determine error indicators indicating error locations in a second part of the one or more data words. According to further embodiments of the present invention, a memory device and method of decoding a memory device are also provided.

Abstract translation: 根据本发明的实施例，提供了一种用于存储器件的解码器。 解码器包括错误检测电路，其被配置为将一个或多个数据字的向量与奇偶校验矩阵相乘以确定多个校正子值，并且通过将校正子向量与校正子矩阵的倒数相乘来生成多个系数; 以及错误校正电路，被配置为对所述多个系数的第一部分执行Chien搜索以确定指示所述一个或多个数据字的第一部分中的错误位置的错误指示符，并且随后在所述多个系数的第二部分上 以确定指示所述一个或多个数据字的第二部分中的错误位置的错误指示符。 根据本发明的另外的实施例，还提供了存储器件和存储器件解码方法。

公开(公告)号：US09454428B2

公开(公告)日：2016-09-27

申请号：US14554577

申请日：2014-11-26

Applicant: Agency for Science, Technology and Research

Inventor： Kui Cai ,  Zhiliang Qin ,  Xueqiang Wang

IPC: H03M13/00 ,  G06F11/10 ,  H03M13/45 ,  G11C11/16 ,  H03M13/15

CPC classification number: G06F11/1012 ,  G11C11/16 ,  G11C11/161 ,  H03M13/152 ,  H03M13/451 ,  H03M13/458

Abstract: There is provided an error correction method for a non-volatile memory. The method includes receiving a codeword read from the non-volatile memory, computing a reliability information for each bit of the codeword received, and performing a reduced-complexity soft-decision decoding (SDD) technique to decode the received codeword. In particular, the SDD technique includes forming a set of test patterns based on the reliability data, and determining whether to perform a HDD of a test pattern in the set of test patterns based on a distance between the test pattern and a candidate pattern. There is also provided an error correction module for a non-volatile memory and a memory system incorporating the error correction module.

Abstract translation: 提供了用于非易失性存储器的纠错方法。 该方法包括接收从非易失性存储器读取的码字，计算接收到的码字的每个比特的可靠性信息，并执行降低复杂度的软判决解码（SDD）技术来解码所接收的码字。 特别地，SDD技术包括基于可靠性数据形成一组测试图案，并且基于测试图案和候选图案之间的距离来确定是否在该组测试图案中执行测试图案的HDD。 还提供了用于非易失性存储器的错误校正模块和包含纠错模块的存储器系统。