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    Method for the formation of interconnects and landing pads having a thin, conductive film underlying the plug or an associated contact of via hole
    2.
    发明授权
    Method for the formation of interconnects and landing pads having a thin, conductive film underlying the plug or an associated contact of via hole 失效
    用于形成互连件和着陆垫的方法，其具有位于插头下方的薄导电膜或通孔的相关接触件

    公开(公告)号：US5514622A

    公开(公告)日：1996-05-07

    申请号：US297626

    申请日：1994-08-29

    申请人： Johnathan G. Bornstein ,  Roger Caldwell

    发明人： Johnathan G. Bornstein ,  Roger Caldwell

    IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L21/283

    CPC分类号： H01L21/285 ,  H01L21/76895

    摘要： The present invention provides a method for the formation of interconnects and landing pads having a thin, conductive film underlying the plug of an associated contact or via hole. In accordance with the preferred embodiment of the present invention, a silicon substrate is provided having at least one device region formed at the surface of the substrate. An insulating layer is deposited over the substrate having at least one contact hole formed through the insulating layer to expose the device region. A first blanket layer of titanium is deposited as a tungsten adhesion layer over the insulating layer and the exposed device region within the contact hole. A second blanket layer of titanium-tungsten or titanium-nitride is then deposited as a tungsten barrier layer over the adhesion layer. Subsequently, a blanket contact plug layer comprising tungsten is deposited over the barrier layer by chemical vapor deposition. Both the contact plug layer and the barrier layer are then removed from the surface of the adhesion layer everywhere except within the contact hole by a selective etch back process wherein a selectivity between tungsten and titanium of at least 5:1 is achieved. Next, the exposed portions of the adhesion layer are patterned with a mask and etched to remove those portions of the adhesion layer not covered by the mask, thus converting the adhesion layer into a thin film interconnect or landing pad underlying the contact plug of the associated contact hole.

    摘要翻译： 本发明提供一种用于形成互连件和着陆垫的方法，其具有位于相关接触件或通孔的插塞下方的薄的导电膜。 根据本发明的优选实施例，提供了硅衬底，其具有形成在衬底表面的至少一个器件区域。 绝缘层沉积在衬底上，其具有通过绝缘层形成的至少一个接触孔，以暴露器件区域。 在绝缘层和接触孔内的暴露的器件区域上沉积第一层覆盖层作为钨粘合层。 然后将钛 - 钨或氮化钛的第二覆盖层沉积在粘附层上作为钨阻挡层。 随后，通过化学气相沉积在阻挡层上沉积包含钨的覆盖接触塞层。 然后通过选择性回蚀法将接触塞层和阻挡层两者从粘合层的表面除去，除了在接触孔内，其中钨和钛之间的选择性至少为5:1。 接下来，用掩模对粘合层的暴露部分进行图案化并蚀刻以去除未被掩模覆盖的粘合层的那些部分，从而将粘附层转变成相关联的接触塞下面的薄膜互连或着陆垫 接触孔。

    Method of patterning sub-0.25&lgr; line features with high transmission, “attenuated” phase shift masks
    3.
    发明授权
    Method of patterning sub-0.25&lgr; line features with high transmission, “attenuated” phase shift masks 有权
    使用高透射“衰减”相移掩模图案化0.25Lambline线特征的方法

    公开(公告)号：US06482555B2

    公开(公告)日：2002-11-19

    申请号：US09976336

    申请日：2001-10-15

    申请人： J. Fung Chen ,  Roger Caldwell ,  Tom Laidig ,  Kurt E. Wampler

    发明人： J. Fung Chen ,  Roger Caldwell ,  Tom Laidig ,  Kurt E. Wampler

    IPC分类号： G03F900

    CPC分类号： G03F1/32 ,  G03F1/26 ,  G03F1/34 ,  G03F1/36

    摘要： A method for making a mask for optically transferring a lithographic pattern corresponding to an integrated circuit from the mask onto a semiconductor substrate by use of an optical exposure tool. The method includes the steps of de-composing the existing mask patterns into arrays of “imaging elements.” The imaging elements are &pgr;-phase shifted and are separated by non-phase shifting and sub-resolution elements referred to as anti-scattering bars (ASBs). In essence, the ASBs are utilized to de-compose the larger-than-minimum-width mask features to form “halftone-like” imaging patterns. The placement of the ASBs and the width thereof are such that none of the &pgr;-phase shifting elements are individually resolvable, but together they form patterns substantially similar to the intended mask features.

    摘要翻译： 一种制造掩模的方法，该掩模用于通过使用光学曝光工具将对应于集成电路的光刻图案从掩模光学转移到半导体衬底上。 该方法包括以下步骤：将现有的掩模图案组合成“成像元件”的阵列。 成像元件是pi相位偏移的，并被称为抗散射棒（ASB）的非相移和次分辨率元件分开。 实质上，ASB用于去除大于最小宽度的掩模特征以形成“半色调”成像图案。 ASB的放置和其宽度使得没有一个pi相移元件是可单独分辨的，但是它们一起形成基本上类似于预期掩模特征的图案。

    Method of patterning sub-0.25 lambda line features with high transmission, “attenuated” phase shift masks
    6.
    发明授权
    Method of patterning sub-0.25 lambda line features with high transmission, “attenuated” phase shift masks 有权
    使用高透射“衰减”相移掩模图案化0.25μm线的特征

    公开(公告)号：US06312854B1

    公开(公告)日：2001-11-06

    申请号：US09270052

    申请日：1999-03-16

    申请人： J. Fung Chen ,  Roger Caldwell ,  Tom Laidig ,  Kurt E. Wampler

    发明人： J. Fung Chen ,  Roger Caldwell ,  Tom Laidig ,  Kurt E. Wampler

    IPC分类号： G03F900

    CPC分类号： G03F1/32 ,  G03F1/26 ,  G03F1/34 ,  G03F1/36

    摘要： A method for making a mask for optically transferring a lithographic pattern corresponding to an integrated circuit from the mask onto a semiconductor substrate by use of an optical exposure tool. The method includes the steps of de-composing the existing mask patterns into arrays of “imaging elements.” The imaging elements are &pgr;-phase shifted and are separated by non-phase shifting and sub-resolution elements referred to as anti-scattering bars (ASBs). In essence, the ASBs are utilized to de-compose the larger-than-minimum-width mask features to form “halftone-like” imaging patterns. The placement of the ASBs and the width thereof are such that none of the &pgr;-phase shifting elements are individually resolvable, but together they form patterns substantially similar to the intended mask features.

    摘要翻译： 一种制造掩模的方法，该掩模用于通过使用光学曝光工具将对应于集成电路的光刻图案从掩模光学转移到半导体衬底上。 该方法包括以下步骤：将现有的掩模图案组合成“成像元件”的阵列。 成像元件是pi相位偏移的，并被称为抗散射棒（ASB）的非相移和次分辨率元件分开。 实质上，ASB用于去除大于最小宽度的掩模特征以形成“半色调”成像图案。 ASB的放置和其宽度使得没有一个pi相移元件是可单独分辨的，但是它们一起形成基本上类似于预期掩模特征的图案。

    Hybrid phase-shift mask
    7.
    发明授权
    Hybrid phase-shift mask 有权
    混合相移掩模

    公开(公告)号：US06835510B2

    公开(公告)日：2004-12-28

    申请号：US10662365

    申请日：2003-09-16

    申请人： Jang Fung Chen ,  Roger Caldwell ,  Thomas Laidig ,  Kurt E. Wampler

    发明人： Jang Fung Chen ,  Roger Caldwell ,  Thomas Laidig ,  Kurt E. Wampler

    IPC分类号： G03F900

    CPC分类号： G03F1/32 ,  G03F1/26 ,  G03F1/30 ,  G03F1/34

    摘要： A method of forming a hybrid mask for optically transferring a lithographic pattern corresponding to an integrated circuit from the mask onto a semiconductor substrate by use of an optical exposure tool. The method includes the steps of forming at least one non-critical feature on the mask utilizing one of a low-transmission phase-shift mask (pattern) and a non-phase shifting mask (pattern), and forming at least one critical feature on the mask utilizing a high-transmission phase-shift mask (pattern).

    摘要翻译： 一种形成用于通过使用光学曝光工具将对应于集成电路的光刻图案从掩模光学转移到半导体衬底上的混合掩模的方法。 该方法包括以下步骤：使用低透射相移掩模（图案）和非相移掩模（图案）之一在掩模上形成至少一个非关键特征，并且形成至少一个关键特征 该掩模利用高透射相移掩模（图案）。