公开(公告)号：US20110102442A1

公开(公告)日：2011-05-05

申请号：US12611992

申请日：2009-11-04

申请人： Ahmed Rafeek Bin Ahmad Ibrahim ,  Wee Hoo Cheah

发明人： Ahmed Rafeek Bin Ahmad Ibrahim ,  Wee Hoo Cheah

IPC分类号： G06T1/00 ,  G09G5/36

CPC分类号： H04N5/76 ,  H04N5/4448 ,  H04N5/781

摘要： Screen recording may be implemented with better security, performance, power savings and cost without the need of additional software to support the screen recording feature, in some embodiments, by using a keyboard, video, mouse functionality already provided in a computer system chipset on a motherboard. Frames of video may be stored on that system or, in some cases, may be selectively provided to a local area network.

摘要翻译： 在一些实施例中，通过使用已经在计算机系统芯片组中提供的键盘，视频，鼠标功能，可以在更好的安全性，性能，功率节省和成本的情况下实现屏幕录制，而不需要额外的软件来支持屏幕录制功能 母板。 视频的帧可以存储在该系统上，或者在某些情况下可以选择性地提供给局域网。

公开(公告)号：US20120151109A1

公开(公告)日：2012-06-14

申请号：US12928334

申请日：2010-12-09

申请人： Wee Hoo Cheah ,  Chun Hung Pang ,  Kuan Loon Tan

发明人： Wee Hoo Cheah ,  Chun Hung Pang ,  Kuan Loon Tan

IPC分类号： G06F13/36

CPC分类号： G06F13/4031 ,  G06F1/3253 ,  Y02D10/151

摘要： In some embodiments, a serial bus interface circuit includes at least two serial ports, a memory to store a relationship between serial bus addresses and the at least two serial ports, and a controller to control access to the at least two serial ports. The controller may be configured to receive an access request for a serial bus address, determine a first port of the at least two serial ports corresponding to the serial bus address using the relationships stored in the memory, and disable a second port of the at least two serial ports. Other embodiments are disclosed and claimed.

摘要翻译： 在一些实施例中，串行总线接口电路包括至少两个串行端口，存储器，用于存储串行总线地址与至少两个串行端口之间的关系，以及控制器，用于控制对至少两个串行端口的访问。 控制器可以被配置为接收对串行总线地址的访问请求，使用存储在存储器中的关系确定对应于串行总线地址的至少两个串行端口的第一端口，并且禁用至少第二端口 两个串口 公开和要求保护其他实施例。

公开(公告)号：US10198333B2

公开(公告)日：2019-02-05

申请号：US13997182

申请日：2010-12-23

申请人： Mark B. Trobough ,  Keshavan K. Tiruvallur ,  Chinna B. Prudvi ,  Christian E. Iovin ,  David W. Grawrock ,  Jay J. Nejedlo ,  Ashok N. Kabadi ,  Travis K. Goff ,  Evan J. Halprin ,  Kapila B. Udawatta ,  Jiun Long Foo ,  Wee Hoo Cheah ,  Vui Yong Liew ,  Selvakumar Raja Gopal ,  Yuen Tat Lee ,  Samie B. Samaan ,  Kip C. Killpack ,  Neil Dobler ,  Nagib Z. Hakim ,  Brian Meyer ,  William H. Penner ,  John L. Baudrexl ,  Russell J. Wunderlich ,  James J. Grealish ,  Kyle Markley ,  Timothy S. Storey ,  Loren J. McConnell ,  Lyle E. Cool ,  Mukesh Kataria ,  Rahima K. Mohammed ,  Tieyu Zheng ,  Yi Amy Xia ,  Ridvan A. Sahan ,  Arun R. Ramadorai ,  Priyadarsan Patra ,  Edwin E. Parks ,  Abhijit Davare ,  Padmakumar Gopal ,  Bruce Querbach ,  Hermann W. Gartler ,  Keith Drescher ,  Sanjay S. Salem ,  David C. Florey

发明人： Mark B. Trobough ,  Keshavan K. Tiruvallur ,  Chinna B. Prudvi ,  Christian E. Iovin ,  David W. Grawrock ,  Jay J. Nejedlo ,  Ashok N. Kabadi ,  Travis K. Goff ,  Evan J. Halprin ,  Kapila B. Udawatta ,  Jiun Long Foo ,  Wee Hoo Cheah ,  Vui Yong Liew ,  Selvakumar Raja Gopal ,  Yuen Tat Lee ,  Samie B. Samaan ,  Kip C. Killpack ,  Neil Dobler ,  Nagib Z. Hakim ,  Brian Meyer ,  William H. Penner ,  John L. Baudrexl ,  Russell J. Wunderlich ,  James J. Grealish ,  Kyle Markley ,  Timothy S. Storey ,  Loren J. McConnell ,  Lyle E. Cool ,  Mukesh Kataria ,  Rahima K. Mohammed ,  Tieyu Zheng ,  Yi Amy Xia ,  Ridvan A. Sahan ,  Arun R. Ramadorai ,  Priyadarsan Patra ,  Edwin E. Parks ,  Abhijit Davare ,  Padmakumar Gopal ,  Bruce Querbach ,  Hermann W. Gartler ,  Keith Drescher ,  Sanjay S. Salem ,  David C. Florey

IPC分类号： G06F11/273 ,  G06F11/267

摘要： An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.

公开(公告)号：US20190139422A1

公开(公告)日：2019-05-09

申请号：US16235164

申请日：2018-12-28

申请人： Wee Hoo Cheah ,  David W. Browning

发明人： Wee Hoo Cheah ,  David W. Browning

IPC分类号： G08G5/00 ,  G01C21/00

摘要： A drone positioning system includes a processor subsystem and memory comprising instructions, which when executed by the processor subsystem, cause the processor subsystem to perform the operations comprising: transmitting, from an operation drone, a request message to a plurality of companion drones; receiving a response message from each of the plurality of companion drones, each response message including: a first timestamp indicating when the response message was sent from the corresponding companion drone and a first geoposition of the corresponding companion drone; calculating a first distance to each of the plurality of companion drones using the first timestamps of respective response messages from each of the plurality of companion drones; calculating an estimated geoposition of the operation drone from the respective first distances and the respective first geopositions of the companion drones; and assisting navigation of the operation drone using the estimated geoposition.

公开(公告)号：US20150127983A1

公开(公告)日：2015-05-07

申请号：US13997182

申请日：2010-12-23

申请人： Mark B. Trobough ,  Keshavan K. Tiruvallur ,  Chinna B. Prudvi ,  Christian E. Iovin ,  David W. Grawrock ,  Jay J. Nejedlo ,  Ashok N. Kabadi ,  Travis K. Goff ,  Evan J. Halprin ,  Kapila B. Udawatta ,  Jiun Long Foo ,  Wee Hoo Cheah ,  Vui Yong Liew ,  Selvakumar Raja Gopal ,  Yuen Tat Lee ,  Samie B. Samaan ,  Kip C. Killpack ,  Neil Dobler ,  Nagib Z. Hakim ,  Briar Meyer ,  William H. Penner ,  John L. Baudrexl ,  Russell J. Wunderlich ,  James J. Grealish ,  Kyle Markley ,  Timothy S. Storey ,  Loren J. McConnell ,  Lyle E. Cool ,  Mukesh Kataria ,  Rahima K. Mohammed ,  Tieyu Zheng ,  Yi Amy Xia ,  Ridvan A. Sahan ,  Arun R. Ramadorai ,  Priyadarsan Patra ,  Edwin E. Parks ,  Abhijit Davare ,  Padmakumar Gopal ,  Bruce Querbach ,  Hermann W. Gartler ,  Keith Drescher ,  Sanjay S. Salem ,  David C. Florey

发明人： Mark B. Trobough ,  Keshavan K. Tiruvallur ,  Chinna B. Prudvi ,  Christian E. Iovin ,  David W. Grawrock ,  Jay J. Nejedlo ,  Ashok N. Kabadi ,  Travis K. Goff ,  Evan J. Halprin ,  Kapila B. Udawatta ,  Jiun Long Foo ,  Wee Hoo Cheah ,  Vui Yong Liew ,  Selvakumar Raja Gopal ,  Yuen Tat Lee ,  Samie B. Samaan ,  Kip C. Killpack ,  Neil Dobler ,  Nagib Z. Hakim ,  Briar Meyer ,  William H. Penner ,  John L. Baudrexl ,  Russell J. Wunderlich ,  James J. Grealish ,  Kyle Markley ,  Timothy S. Storey ,  Loren J. McConnell ,  Lyle E. Cool ,  Mukesh Kataria ,  Rahima K. Mohammed ,  Tieyu Zheng ,  Yi Amy Xia ,  Ridvan A. Sahan ,  Arun R. Ramadorai ,  Priyadarsan Patra ,  Edwin E. Parks ,  Abhijit Davare ,  Padmakumar Gopal ,  Bruce Querbach ,  Hermann W. Gartler ,  Keith Drescher ,  Sanjay S. Salem ,  David C. Florey

IPC分类号： G06F11/273

CPC分类号： G06F11/2733 ,  G06F11/267

摘要： An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and de-bug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.

摘要翻译： 这里描述了一种用于提供测试，验证和调试架构的装置和方法。 在目标或基础级别，硬件（测试设计或DFx）被设计并集成在硅部件中。 控制器可以提供对这种钩子的抽象访问，例如通过抽象层来抽象硬件DFx的低级细节。 此外，通过接口（如API）的抽象层向更高级的软件/表示层提供服务，例程和数据结构，这些层能够收集测试数据，以便对被测单元/平台进行验证和调试。 此外，该架构可能提供对测试架构的分层（多级）安全访问。 此外，可以通过使用统一的双向测试访问端口来简化对平台的测试架构的物理访问，同时还可能允许远程访问执行被测部件/平台的远程测试和脱离。 本质上描述了一个完整的测试架构栈，用于电子部件，设备和平台的测试，验证和调试。

公开(公告)号：US20140108845A1

公开(公告)日：2014-04-17

申请号：US14134166

申请日：2013-12-19

申请人： Wee Hoo Cheah ,  Chun Hung Pang ,  Kuan Loon Tan

发明人： Wee Hoo Cheah ,  Chun Hung Pang ,  Kuan Loon Tan

IPC分类号： G06F1/32

CPC分类号： G06F13/4031 ,  G06F1/3253 ,  Y02D10/151

摘要： In some embodiments, a serial bus interface circuit includes at least two serial ports, a memory to store a relationship between serial bus addresses and the at least two serial ports, and a controller to control access to the at least two serial ports. The controller may be configured to receive an access request for a serial bus address, determine a first port of the at least two serial ports corresponding to the serial bus address using the relationships stored in the memory, and disable a second port of the at least two serial ports. Other embodiments are disclosed and claimed.

摘要翻译： 在一些实施例中，串行总线接口电路包括至少两个串行端口，存储器，用于存储串行总线地址与至少两个串行端口之间的关系，以及控制器，用于控制对至少两个串行端口的访问。 控制器可以被配置为接收对串行总线地址的访问请求，使用存储在存储器中的关系确定对应于串行总线地址的至少两个串行端口的第一端口，并且禁用至少第二端口 两个串口 公开和要求保护其他实施例。

公开(公告)号：US08621129B2

公开(公告)日：2013-12-31

申请号：US12928334

申请日：2010-12-09

申请人： Wee Hoo Cheah ,  Chun Hung Pang ,  Kuan Loon Tan

发明人： Wee Hoo Cheah ,  Chun Hung Pang ,  Kuan Loon Tan

IPC分类号： G06F13/36 ,  G06F13/40

CPC分类号： G06F13/4031 ,  G06F1/3253 ,  Y02D10/151

摘要： In some embodiments, a serial bus interface circuit includes at least two serial ports, a memory to store a relationship between serial bus addresses and the at least two serial ports, and a controller to control access to the at least two serial ports. The controller may be configured to receive an access request for a serial bus address, determine a first port of the at least two serial ports corresponding to the serial bus address using the relationships stored in the memory, and disable a second port of the at least two serial ports. Other embodiments are disclosed and claimed.

摘要翻译： 在一些实施例中，串行总线接口电路包括至少两个串行端口，存储器，用于存储串行总线地址与至少两个串行端口之间的关系，以及控制器，用于控制对至少两个串行端口的访问。 控制器可以被配置为接收对串行总线地址的访问请求，使用存储在存储器中的关系确定对应于串行总线地址的至少两个串行端口的第一端口，并且禁用至少第二端口 两个串口 公开和要求保护其他实施例。