公开(公告)号：US07328371B1

公开(公告)日：2008-02-05

申请号：US10966466

申请日：2004-10-15

申请人： Vydhyanathan Kalyanasundharam ,  William A. Hughes ,  Philip E. Madrid ,  Scott A. White ,  Ajay Naini

发明人： Vydhyanathan Kalyanasundharam ,  William A. Hughes ,  Philip E. Madrid ,  Scott A. White ,  Ajay Naini

IPC分类号： G06F11/00

CPC分类号： G06F11/1641 ,  G06F11/1679 ,  G06F11/181 ,  G06F11/184 ,  G06F2201/845

摘要： In one embodiment, a node comprises a plurality of processor cores and a node controller coupled to the processor cores. The node controller is configured to route communications from the processor cores to other devices in a computer system. The node controller comprises a circuit coupled to receive the communications from the processor cores. In a redundant execution mode in which at least a first processor core is redundantly executing code that a second processor core is also executing, the circuit is configured to compare communications from the first processor core to communications from the second processor core to verify correct execution of the code. In some embodiments, the processor cores and the node controller may be integrated onto a single integrated circuit chip as a CMP. A similar method is also contemplated.

摘要翻译： 在一个实施例中，节点包括多个处理器核和耦合到处理器核的节点控制器。 节点控制器被配置为将来自处理器核心的通信路由到计算机系统中的其他设备。 节点控制器包括耦合以从处理器核心接收通信的电路。 在冗余执行模式中，其中至少第一处理器核冗余地执行第二处理器核也正在执行的代码，该电路被配置为将来自第一处理器核心的通信与来自第二处理器核心的通信进行比较，以验证是否正确执行 代码。 在一些实施例中，处理器核心和节点控制器可以作为CMP集成到单个集成电路芯片上。 也可以考虑类似的方法。

公开(公告)号：US06603333B2

公开(公告)日：2003-08-05

申请号：US09731327

申请日：2000-12-05

申请人： James Vinh ,  Pranjal Srivastava ,  Robert S. Grondalski ,  Ajay Naini

发明人： James Vinh ,  Pranjal Srivastava ,  Robert S. Grondalski ,  Ajay Naini

IPC分类号： H03K1996

CPC分类号： H03K19/0963

摘要： A method and apparatus for protecting dynamic logic circuits from the effects of noise at the inputs to the dynamic logic circuits is disclosed. Parallel current flow or evaluate paths which couple an output node through a common node to a low voltage or ground rail include extra transistors in the current flow or evaluate path to allow the inputs to be protected while maintaining the operation and integrity of the circuit.

公开(公告)号：US5523961A

公开(公告)日：1996-06-04

申请号：US330776

申请日：1994-10-28

申请人： Ajay Naini

发明人： Ajay Naini

IPC分类号： H03M7/24 ,  G06F7/00 ,  G06F7/38

CPC分类号： H03M7/24

摘要： Exponent conversion logic implements floating point exponent conversion of single/double precision to an extended format (IEEE 754 standard), such as in the floating point unit of an x86 processor. The SP (single precision)/DP (double precision) to EP (extended precision exponent conversion technique avoids using an adder (with the attendant propagation delay). For SP exponents (8 bit), the exponent conversion logic implements conversion to EP format (15 bits) as follows (FIG. 3a): (a) transferring the 7 LSB (least significant bits) of the SP exponent (41) as the corresponding 7 LSBs of the EP format (42), (b) inverting the MSB (most significant bit) of the SP exponent and using it as the 7 next most significant bits of the EP format, and (c) transferring the MSB of the SP exponent of the MSB of the EP. The operation for converting DP exponents (11 bits) to EP format is analogous. The same exponent conversion techniques are used to reconvert extended format exponents to single and double precision exponents.

摘要翻译： 指数转换逻辑将单/双精度的浮点指数转换实现为扩展格式（IEEE 754标准），例如x86处理器的浮点单元。 SP（单精度）/ DP（双精度）到EP（扩展精度指数转换技术避免使用加法器（伴随传播延迟）对于SP指数（8位），指数转换逻辑实现转换为EP格式 15位）如下（图3a）：（a）将SP指数（41）的7个LSB（最低有效位）作为EP格式（42）的相应7个LSB传送，（b）将MSB 最高有效位），并将其用作EP格式的第7个最高有效位，（c）传送EP的MSB的SP指数的MSB，用于转换DP指数（11位 ）到EP格式是类似的，使用相同的指数转换技术将扩展格式指数重新转换为单精度指数和双精度指数。

公开(公告)号：US06954912B2

公开(公告)日：2005-10-11

申请号：US10150847

申请日：2002-05-17

申请人： Pranjal Srivastava ,  Ajay Naini ,  Atul Dhablania

发明人： Pranjal Srivastava ,  Ajay Naini ,  Atul Dhablania

IPC分类号： G06F11/18 ,  G01R31/317 ,  G01R31/3183 ,  G01R31/3185 ,  H03K19/096 ,  G06F17/50

CPC分类号： G01R31/31705 ,  G01R31/31704 ,  G01R31/318392 ,  G01R31/318502

摘要： Error detection apparatus and methods for dynamic logic are provided. Circuit errors are detected by comparing true and complement signals to ensure they are in fact complementary signals. A pseudocomplement technique is used to implement an adder in which distinct logic cones generate the true and complement carry signals. Other embodiments comprising additional features, such as shared logic cone decomposition, are also provided.

摘要翻译： 提供了用于动态逻辑的错误检测装置和方法。 通过比较真实和补码信号来检测电路错误，以确保它们实际上是互补信号。 伪互补技术用于实现加法器，其中不同的逻辑锥产生真和进位信号。 还提供了包括附加特征（例如共享逻辑锥分解）的其他实施例。

公开(公告)号：US5220525A

公开(公告)日：1993-06-15

申请号：US787477

申请日：1991-11-04

申请人： William C. Anderson ,  Ajay Naini

发明人： William C. Anderson ,  Ajay Naini

IPC分类号： G06F7/52

CPC分类号： G06F7/5338

摘要： A recorded iterative multiplier (20) performs an unsigned multiplication operation quickly and with a minimal amount of added circuitry. Multiplier (20) includes a Modified Booth recoder (34) and a plurality of multiplexors (24, 26, 28, 30, and 32) to provide a plurality of partial products. An additional partial product typically generated during a first iteration of the multiplication operation is provided to a multiplexor (44) and a remaining portion of partial products are provided to a summation tree (40) having a symmetrical circuit layout. [Multiplexor (44) stores the additional partial product until summation tree (40) has processed the remaining partial products to provide a first sum.] When summation tree (40) has processed the remaining partial products to provide a first sum, multiplexor (44) provides the additional partial product to a carry save adder (42). The first sum is added to the additional partial product in [a carry-save] adder (42) to provide a first portion of a product. During a second iteration of the multiplication operation, an additional partial product is not generated, and summation tree (40) provides the second portion of the multiplication product. The first and second portions are then summed in carry-save adder (42) to provide the multiplication product.

摘要翻译： 记录的迭代乘法器（20）快速执行无符号乘法运算，并以最小量的附加电路执行。 乘法器（20）包括修改的展位重新编码器（34）和多个多路复用器（24,26,28,30和32），以提供多个部分乘积。 通常在乘法运算的第一迭代期间产生的附加部分乘积被提供给多路复用器（44），并且部分乘积的剩余部分被提供给具有对称电路布局的求和树（40）。 多路复用器（44）存储额外的部分乘积，直到求和树（40）已经处理剩余的部分乘积以提供第一和。]当求和树（40）已经处理剩余的部分乘积以提供第一和时，多路复用器 ）向进位保存加法器（42）提供额外的部分乘积。 将第一和加到[进位保存]加法器（42）中的附加部分乘积以提供乘积的第一部分。 在乘法运算的第二次迭代期间，不产生附加的部分乘积，并且求和树（40）提供乘积的第二部分。 然后，第一和第二部分在进位保存加法器（42）中相加以提供乘积。

公开(公告)号：US06542423B1

公开(公告)日：2003-04-01

申请号：US09955619

申请日：2001-09-18

申请人： Vydhyanathan Kalyanasundharam ,  Ajay Naini

发明人： Vydhyanathan Kalyanasundharam ,  Ajay Naini

IPC分类号： G11C700

CPC分类号： G11C7/1015 ,  G11C7/1036 ,  G11C7/12 ,  G11C15/04 ,  G11C2207/007

摘要： A register array system including a first number of rows by a second number of columns of data registers, a read line, a read bit line, and a single pull down device corresponding to each data register in each column of data registers and configured to discharge, in response to being turned on, the read bit line corresponding to the column of data registers. The pull down device corresponding to a data register is only turned in response to a clock signal, a read enable signal, and the data stored in the data register each having a high value. Therefore, the capacitance associated with the read bit line corresponding to a column of data registers stays at the same capacitance value during the precharging phase and during a multi-hot condition. The problem of voltage droop caused by charging sharing in a multi-hot condition is thus eliminated.

摘要翻译： 一种寄存器阵列系统，其包括数据寄存器的第二数量列的第一数量的行，读取行，读取位线和对应于每列数据寄存器中的每个数据寄存器的单个下拉器件，并且被配置为放电 响应于被接通，对应于数据列的读位线寄存器。 对应于数据寄存器的下拉装置仅响应于时钟信号，读使能信号和存储在每个具有高值的数据寄存器中的数据而被转换。 因此，与数据寄存器列对应的读位线相关的电容在预充电阶段和多热条件期间保持在相同的电容值。 因此消除了在多热条件下的充电共享引起的电压下降的问题。

公开(公告)号：US06209083B1

公开(公告)日：2001-03-27

申请号：US08942236

申请日：1997-10-01

申请人： Ajay Naini ,  Robert D. Maher, III

发明人： Ajay Naini ,  Robert D. Maher, III

IPC分类号： G06F1300

CPC分类号： G06F9/3885 ,  G06F9/30101 ,  G06F9/3861 ,  G06F9/3867

摘要： An FPU configured to operate in normal and fast modes. In normal mode, floating point instructions are stalled in an address calculation unit of the processor until the previously issued floating point instruction has cleared the FPU, thereby indicating that the previous floating point instruction will not have an exception. In fast mode, the address calculation unit will issue a next floating point instruction to the FPU, where it is held in a 4-deep instruction queue, regardless of whether a prior instruction has cleared. By eliminating stalls in the instruction execution pipeline caused by floating point instructions being held in the address calculation unit pending clearance of the prior floating point instruction, the instruction execution pipeline may issue floating point instructions to the FPU at a faster rate.

摘要翻译： FPU配置为以正常和快速模式运行。 在正常模式下，在处理器的地址计算单元中停止浮点指令，直到先前发出的浮点指令清除了FPU，从而指示先前的浮点指令不会有异常。 在快速模式下，地址计算单元将向FPU发出下一个浮点指令，无论先前的指令是否清除，地址计算单元将保持在四深指令队列中。 通过消除指令执行流水线中由于浮动指令被保持在地址计算单元中等待先前浮点指令的清除而引起的停顿，指令执行流水线可以以更快的速率向FPU发出浮点指令。

公开(公告)号：US5276635A

公开(公告)日：1994-01-04

申请号：US69646

申请日：1993-06-01

申请人： Ajay Naini ,  William C. Anderson

发明人： Ajay Naini ,  William C. Anderson

IPC分类号： G06F7/50 ,  G06F7/508

CPC分类号： G06F7/508

摘要： A carry look-ahead (CLA) adder accommodates a late carry-in from a low-order external 32-bit adder to enable a 96-bit addition to be performed in the same time in which the CLA adder (60) performs a 64-bit addition. Within each adder slice, intermediate group propagate and group generate terms are generated for each bit location in the adder (60), while the adder simultaneously generates an n-bit group propagate and group generate term. The intermediate group propagate and group generate terms are combined with carry-in terms to generate, in parallel, local carry-out terms within each adder slice. The local carry-out terms and intermediate group propagate and group generate terms are used to form a carry chain path which allows the adder to delay the carry-in of an external carry term.

摘要翻译： 进位预读（CLA）加法器适用于从低位外部32位加法器的延迟进位，以使得能够在CLA加法器（60）执行64位的同一时间执行96位加法运算 - 除此之外。 在每个加法器切片内，对加法器（60）中的每个比特位置生成中间组传播和组生成项，而加法器同时生成n位组传播和组生成项。 中间组传播和组生成项与进位项组合，以在每个加法器切片内并行生成局部进位项。 本地进位项和中间组传播和组生成术语用于形成进位链路径，允许加法器延迟外部进位项的进位。

公开(公告)号：US5265043A

公开(公告)日：1993-11-23

申请号：US9435

申请日：1993-01-27

申请人： Ajay Naini ,  William C. Anderson ,  Lisa J. Craft

发明人： Ajay Naini ,  William C. Anderson ,  Lisa J. Craft

IPC分类号： G06F7/52 ,  G06F7/533

CPC分类号： G06F7/5318 ,  G06F7/5338

摘要： A Wallace tree multiplier array (40) performs multiply operations using operands received via a data path (42) having a predetermined height. Rows of carry save adders (CSAs 15'-19") add sets of partial products to generate sets of intermediate summands, which are recursively added to generate a set of final summands. A first group of CSAs form a column which is placed along an axis parallel to the data path (42), and are used to compute a more significant number of bits of each of the summands. The column height of the first group of CSAs is equal to and aligned with the height of the data path (42). A second group of CSAs are placed along an axis perpendicular to the column formed by the first group of CSAs, thereby minimizing the dimension of the multiplier along the data path. The second group of CSAs compute a less significant number of bits of the summands.

摘要翻译： 华莱士树乘法器阵列（40）使用经由具有预定高度的数据路径（42）接收的操作数来执行乘法运算。 进位保存加法器（CSA 15'-19“）的行添加一组部分乘积以生成中间求和集，其被递归地添加以生成一组最终的求和。 第一组CSA形成沿着与数据路径（42）平行的轴放置的列，并且用于计算每个总和的更多有效位数。 第一组CSA的列高度等于并与数据路径（42）的高度对齐。 第二组CSA沿着垂直于由第一组CSA组形成的列的轴放置，从而使沿着数据路径的乘法器的尺寸最小化。 第二组CSA计算总和的比特数较少。