公开(公告)号：US09063663B2

公开(公告)日：2015-06-23

申请号：US12936176

申请日：2010-09-21

申请人： Akifumi Suzuki ,  Atsushi Kawamura ,  Junji Ogawa

发明人： Akifumi Suzuki ,  Atsushi Kawamura ,  Junji Ogawa

IPC分类号： G06F12/00 ,  G06F3/06 ,  G06F13/00

CPC分类号： G06F3/064 ,  G06F3/0608 ,  G06F3/0688

摘要： The flash memory controller compresses data in response to a write request. On condition that there is a compression effect with respect to the compressed data, the flash memory controller writes the compressed data to the base area of a physical block of a flash memory. As physical pages assigned to the physical block, the flash memory controller reduces the physical pages assigned to the base area from 102 down to 59, and increases the physical pages assigned to the update area from 26 up to 69. Therefore, it is possible to suppress exhaustion of physical pages which are assigned to the update area, to reduce the number of erases of the physical block, and to consequently prolong device operating life.

摘要翻译： 闪存控制器响应于写请求压缩数据。 在对压缩数据存在压缩效果的情况下，闪存控制器将压缩数据写入闪存的物理块的基本区域。 作为分配给物理块的物理页面，闪存控制器将分配给基地区的物理页面从102降低到59，并将分配给更新区域的物理页面从26增加到69.因此，可以 抑制分配给更新区域的物理页面的耗尽，减少物理块的擦除次数，从而延长设备的使用寿命。

公开(公告)号：US08984211B2

公开(公告)日：2015-03-17

申请号：US13519462

申请日：2011-12-21

申请人： Tsukasa Shibayama ,  Akifumi Suzuki ,  Nobuhiro Maki ,  Junji Ogawa ,  Masayasu Asano

发明人： Tsukasa Shibayama ,  Akifumi Suzuki ,  Nobuhiro Maki ,  Junji Ogawa ,  Masayasu Asano

IPC分类号： G06F12/02 ,  G11C11/56 ,  G11C29/00

CPC分类号： G06F3/0604 ,  G06F3/0625 ,  G06F3/0644 ,  G06F3/0688 ,  G06F3/0689 ,  G06F12/0246 ,  G06F2212/7207 ,  G11C11/5621 ,  G11C29/82 ,  Y02D10/13

摘要： A storage system, which comprises multiple memory cells and a storage controller, wherein the storage controller manages cell mode information, which either directly or indirectly denotes the number of bits to be stored in multiple memory cells. The cell mode information can be changed in accordance with a request from a management system.

摘要翻译： 一种存储系统，其包括多个存储器单元和存储控制器，其中所述存储控制器管理单元模式信息，所述单元模式信息直接或间接地表示要存储在多个存储器单元中的位数。 小区模式信息可以根据来自管理系统的请求而改变。

公开(公告)号：US20140304451A1

公开(公告)日：2014-10-09

申请号：US13519462

申请日：2011-12-21

申请人： Tsukasa Shibayama ,  Akifumi Suzuki ,  Nobuhiro Maki ,  Junji Ogawa ,  Masayasu Asano

发明人： Tsukasa Shibayama ,  Akifumi Suzuki ,  Nobuhiro Maki ,  Junji Ogawa ,  Masayasu Asano

IPC分类号： G06F12/02

CPC分类号： G06F3/0604 ,  G06F3/0625 ,  G06F3/0644 ,  G06F3/0688 ,  G06F3/0689 ,  G06F12/0246 ,  G06F2212/7207 ,  G11C11/5621 ,  G11C29/82 ,  Y02D10/13

摘要： A storage system, which comprises multiple memory cells and a storage controller, wherein the storage controller manages cell mode information, which either directly or indirectly denotes the number of bits to be stored in multiple memory cells. The cell mode information can be changed in accordance with a request from a management system.

摘要翻译： 一种存储系统，其包括多个存储器单元和存储控制器，其中所述存储控制器管理单元模式信息，所述单元模式信息直接或间接地表示要存储在多个存储器单元中的位数。 小区模式信息可以根据来自管理系统的请求而改变。

公开(公告)号：US08806108B2

公开(公告)日：2014-08-12

申请号：US13141930

申请日：2011-06-07

申请人： Akifumi Suzuki ,  Junji Ogawa

发明人： Akifumi Suzuki ,  Junji Ogawa

IPC分类号： G06F12/00

CPC分类号： G06F3/064 ,  G06F3/0608 ,  G06F3/0616 ,  G06F3/0688 ,  G06F12/0246 ,  G06F2212/1036 ,  G06F2212/401 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7204 ,  G06F2212/7207

摘要： A semiconductor storage apparatus including a flash memory which provides a storage area, and a memory controller which controls the reading and writing of data from and to the flash memory, wherein the storage area of the flash memory is configured from a plurality of write areas, and wherein the memory controller divides the data into a size corresponding to the write area, and changes the starting location of writing the data each time the divided data is written into the write area.

摘要翻译： 一种包括提供存储区域的闪速存储器的半导体存储装置和控制从闪速存储器读取数据的存储器控​​制器，其中闪速存储器的存储区域由多个写入区域构成， 并且其中所述存储器控制器将所述数据划分为与所述写入区域对应的大小，并且每当所述划分的数据被写入所述写入区域时，改变写入所述数据的开始位置。

公开(公告)号：US08898545B2

公开(公告)日：2014-11-25

申请号：US13512804

申请日：2012-05-18

申请人： Takashi Tsunehiro ,  Akifumi Suzuki ,  Junji Ogawa

发明人： Takashi Tsunehiro ,  Akifumi Suzuki ,  Junji Ogawa

IPC分类号： G11C29/00

CPC分类号： G06F11/1068 ,  G11C2029/0411

摘要： A memory controller adds the redundant information that is used to correct an error for each of data of a predetermined length and stores the data into the nonvolatile memory in the case in which data is written to the nonvolatile memory, the memory controller reads data and the redundant information that has been added to the data from the nonvolatile memory in the case in which data is read from the nonvolatile memory, and the memory controller corrects an error based on the redundant information in the case in which the data includes an error. The memory controller stores data that is in a basic unit that is a unit of an error correction configured by the data of a predetermined length and the redundant information that is added to the data of a predetermined length into a plurality of predetermined pages in a dispersed manner.

摘要翻译： 存储器控制器添加用于校正每个预定长度的数据的错误的冗余信息，并且在将数据写入非易失性存储器的情况下将数据存储到非易失性存储器中，存储器控制器读取数据，并且 在从非易失性存储器读取数据的情况下已经添加到来自非易失性存储器的数据的冗余信息，并且存储器控制器在数据包括错误的情况下基于冗余信息来校正错误。 存储器控制器将以预定长度的数据构成的纠错单元的单位的基本单元和附加到预定长度的数据的冗余信息存储到分散的多个预定页面中的数据 方式。

公开(公告)号：US20130311854A1

公开(公告)日：2013-11-21

申请号：US13512804

申请日：2012-05-18

申请人： Takashi Tsunehiro ,  Akifumi Suzuki ,  Junji Ogawa

发明人： Takashi Tsunehiro ,  Akifumi Suzuki ,  Junji Ogawa

IPC分类号： G11C29/04 ,  G06F11/16

CPC分类号： G06F11/1068 ,  G11C2029/0411

摘要： A memory controller adds the redundant information that is used to correct an error for each of data of a predetermined length and stores the data into the nonvolatile memory in the case in which data is written to the nonvolatile memory, the memory controller reads data and the redundant information that has been added to the data from the nonvolatile memory in the case in which data is read from the nonvolatile memory, and the memory controller corrects an error based on the redundant information in the case in which the data includes an error. The memory controller stores data that is in a basic unit that is a unit of an error correction configured by the data of a predetermined length and the redundant information that is added to the data of a predetermined length into a plurality of predetermined pages in a dispersed manner.

摘要翻译： 存储器控制器添加用于校正每个预定长度的数据的错误的冗余信息，并且在将数据写入非易失性存储器的情况下将数据存储到非易失性存储器中，存储器控制器读取数据，并且 在从非易失性存储器读取数据的情况下已经添加到来自非易失性存储器的数据的冗余信息，并且存储器控制器在数据包括错误的情况下基于冗余信息来校正错误。 存储器控制器将以预定长度的数据构成的纠错单元的单位的基本单元和附加到预定长度的数据的冗余信息存储到分散的多个预定页面中的数据 方式。

公开(公告)号：US20120317334A1

公开(公告)日：2012-12-13

申请号：US13141930

申请日：2011-06-07

申请人： Akifumi Suzuki ,  Junji Ogawa

发明人： Akifumi Suzuki ,  Junji Ogawa

IPC分类号： G06F12/00

CPC分类号： G06F3/064 ,  G06F3/0608 ,  G06F3/0616 ,  G06F3/0688 ,  G06F12/0246 ,  G06F2212/1036 ,  G06F2212/401 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7204 ,  G06F2212/7207

摘要： A semiconductor storage apparatus including a flash memory which provides a storage area, and a memory controller which controls the reading and writing of data from and to the flash memory, wherein the storage area of the flash memory is configured from a plurality of write areas, and wherein the memory controller divides the data into a size corresponding to the write area, and changes the starting location of writing the data each time the divided data is written into the write area.

摘要翻译： 一种包括提供存储区域的闪速存储器的半导体存储装置和控制从闪速存储器读取数据的存储器控​​制器，其中闪速存储器的存储区域由多个写入区域构成， 并且其中所述存储器控制器将所述数据划分为与所述写入区域对应的大小，并且每当所述划分的数据被写入所述写入区域时，改变写入所述数据的开始位置。

公开(公告)号：US20120072641A1

公开(公告)日：2012-03-22

申请号：US12936176

申请日：2010-09-21

申请人： Akifumi Suzuki ,  Atsushi Kawamura ,  Junji Ogawa

发明人： Akifumi Suzuki ,  Atsushi Kawamura ,  Junji Ogawa

IPC分类号： G06F12/02

CPC分类号： G06F3/064 ,  G06F3/0608 ,  G06F3/0688

摘要： The flash memory controller compresses data in response to a write request. On condition that there is a compression effect with respect to the compressed data, the flash memory controller writes the compressed data to the base area of a physical block of a flash memory. As physical pages assigned to the physical block, the flash memory controller reduces the physical pages assigned to the base area from 102 down to 59, and increases the physical pages assigned to the update area from 26 up to 69. Therefore, it is possible to suppress exhaustion of physical pages which are assigned to the update area, to reduce the number of erases of the physical block, and to consequently prolong device operating life.

摘要翻译： 闪存控制器响应于写请求压缩数据。 在对压缩数据存在压缩效果的情况下，闪存控制器将压缩数据写入闪存的物理块的基本区域。 作为分配给物理块的物理页面，闪存控制器将分配给基地区的物理页面从102降低到59，并将分配给更新区域的物理页面从26增加到69.因此，可以 抑制分配给更新区域的物理页面的耗尽，减少物理块的擦除次数，从而延长设备的使用寿命。

公开(公告)号：US08832371B2

公开(公告)日：2014-09-09

申请号：US13125618

申请日：2011-04-04

申请人： Go Uehara ,  Koji Sonoda ,  Junji Ogawa

发明人： Go Uehara ,  Koji Sonoda ,  Junji Ogawa

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F11/10 ,  G06F12/02 ,  G06F3/06

CPC分类号： G06F3/064 ,  G06F3/0616 ,  G06F3/0688 ,  G06F11/1044 ,  G06F11/108 ,  G06F12/0246 ,  G06F2211/1059 ,  G06F2212/7211

摘要： A storage system having multiple flash memory packages including flash memory chips and package controllers for controlling access to the flash memory chips is configured such that the package controller receives from a higher-level apparatus, which sends a write request, frequency prediction information that enables prediction of an update frequency with respect to data, which is to be a write target, and when writing data for which a write request has been issued from the higher-level apparatus, control is executed such that data, which is predicted to have a relatively high update frequency based on the frequency prediction information, is preferentially stored in a physical block with the large remaining number of erases in a flash memory chip of flash memory package of the package controller, or such that data, which is predicted to have a relatively low update frequency based on the frequency prediction information, is preferentially stored in a physical block with the small remaining number of erases in a flash memory chip of the flash memory package of the package controller.

摘要翻译： 配置具有多个快闪存储器包的存储系统，包括用于控制对闪速存储器芯片的访问的闪速存储器芯片和封装控制器，使得封装控制器从发送写入请求的更高级别的装置接收能够预测的频率预测信息 相对于作为写入目标的数据的更新频率，并且当写入从较高级别装置发出写请求的数据时，执行控制，使得预测相对于 基于频率预测信息的高更新频率优先存储在具有大量剩余擦除次数的物理块中，所述剩余数量在封装控制器的闪速存储器包的闪速存储器芯片中，或者使得预测具有相对 基于频率预测信息的低更新频率优先存储在具有小rema的物理块中 在包装控制器的闪速存储器包的闪速存储器芯片中引入擦除次数。

公开(公告)号：US20130205070A1

公开(公告)日：2013-08-08

申请号：US13391728

申请日：2012-02-08

申请人： Hideyuki Koseki ,  Junji Ogawa

发明人： Hideyuki Koseki ,  Junji Ogawa

IPC分类号： G06F12/00

CPC分类号： G06F3/0605 ,  G06F3/0608 ,  G06F3/0616 ,  G06F3/0647 ,  G06F3/0659 ,  G06F3/0665 ,  G06F3/067 ,  G06F3/0688

摘要： A storage apparatus is provided with a plurality of nonvolatile semiconductor storage media and a storage controller that is a controller that is coupled to the plurality of semiconductor storage media. The storage controller identifies a first semiconductor storage unit that is at least one semiconductor storage media and a second semiconductor storage unit that is at least one semiconductor storage media and that is provided with a remaining length of life shorter than that of the first semiconductor storage unit based on the remaining life length information that has been acquired. The storage controller moreover identifies a first logical storage region for the first semiconductor storage unit and a second logical storage region that is provided with a write load higher than that of the first logical storage region for the second semiconductor storage unit based on the statistics information that indicates the statistics that is related to a write for every logical storage region. The storage controller reads data from the first logical storage region and the second logical storage region, and writes data that has been read from the first logical storage region to the second logical storage region and/or writes data that has been read from the second logical storage region to the first logical storage region.

摘要翻译： 存储装置设置有多个非易失性半导体存储介质和作为耦合到多个半导体存储介质的控制器的存储控制器。 存储控制器识别作为至少一个半导体存储介质的第一半导体存储单元和至少一个半导体存储介质的第二半导体存储单元，并且具有比第一半导体存储单元短的剩余寿命长度 基于已经获得的剩余寿命信息。 此外，存储控制器还根据统计信息来识别第一半导体存储单元的第一逻辑存储区域和第二逻辑存储区域，该第二逻辑存储区域具有比第二半导体存储单元的第一逻辑存储区域的写入负载更高的写入负载 指示与每个逻辑存储区域的写入相关的统计信息。 存储控制器从第一逻辑存储区域和第二逻辑存储区域读取数据，并且将从第一逻辑存储区域读取的数据写入第二逻辑存储区域和/或写入从第二逻辑存储区域读取的数据 存储区域到第一逻辑存储区域。