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公开(公告)号：US20110303999A1
公开(公告)日：2011-12-15
申请号：US13147871
申请日：2010-02-15
IPC分类号： H01L31/0236
CPC分类号： H01L31/02366 , H01L27/1446 , H01L31/0236 , H01L31/02363 , H01L31/035281 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： Prepared is an n− type semiconductor substrate 1 having a first principal surface 1a and a second principal surface 1b opposed to each other, and having a p+ type semiconductor region 3 formed on the first principal surface 1a side. At least a region opposed to the p+ type semiconductor region 3 in the second principal surface 1b of the n− type semiconductor substrate 1 is irradiated with a pulsed laser beam to form an irregular asperity 10. After formation of the irregular asperity 10, an accumulation layer 11 with an impurity concentration higher than that of the n− type semiconductor substrate 1 is formed on the second principal surface 1b side of the n− type semiconductor substrate 1. After formation of the accumulation layer 11, the n− type semiconductor substrate 1 is subjected to a thermal treatment.
摘要翻译： 制备的n型半导体衬底1具有彼此相对的第一主表面1a和第二主表面1b，并且具有形成在第一主表面1a侧上的p +型半导体区域3。 在n型半导体衬底1的第二主表面1b中至少与p +型半导体区域3相对的区域用脉冲激光束照射以形成不规则凹凸。在形成不规则凹凸10之后，积累 在n型半导体衬底1的第二主表面1b侧上形成杂质浓度高于n型半导体衬底1的层11。在形成蓄积层11之后，n型半导体衬底1 进行热处理。
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公开(公告)号：US08916945B2
公开(公告)日：2014-12-23
申请号：US13147871
申请日：2010-02-15
IPC分类号： H01L27/14 , H01L31/0236 , H01L31/18 , H01L27/144 , H01L31/0352
CPC分类号： H01L31/02366 , H01L27/1446 , H01L31/0236 , H01L31/02363 , H01L31/035281 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： Prepared is an n− type semiconductor substrate 1 having a first principal surface 1a and a second principal surface 1b opposed to each other, and having a p+ type semiconductor region 3 formed on the first principal surface 1a side. At least a region opposed to the p+ type semiconductor region 3 in the second principal surface 1b of the n− type semiconductor substrate 1 is irradiated with a pulsed laser beam to form an irregular asperity 10. After formation of the irregular asperity 10, an accumulation layer 11 with an impurity concentration higher than that of the n− type semiconductor substrate 1 is formed on the second principal surface 1b side of the n type semiconductor substrate 1. After formation of the accumulation layer 11, the n− type semiconductor substrate 1 is subjected to a thermal treatment.
摘要翻译： 制备的n型半导体衬底1具有彼此相对的第一主表面1a和第二主表面1b，并且具有形成在第一主表面1a侧上的p +型半导体区域3。 在n型半导体衬底1的第二主表面1b中至少与p +型半导体区域3相对的区域用脉冲激光束照射以形成不规则凹凸。在形成不规则凹凸10之后，积累 在n型半导体衬底1的第二主表面1b上形成杂质浓度高于n型半导体衬底1的层11。在形成蓄积层11之后，n型半导体衬底1是 进行热处理。
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公开(公告)号：US08564087B2
公开(公告)日：2013-10-22
申请号：US13148091
申请日：2010-02-15
CPC分类号： H01L31/1804 , H01L31/02327 , H01L31/02363 , H01L31/035281 , Y02E10/547
摘要： A semiconductor substrate 2 is dry etched before an insulating layer 4 is exposed, whereby a hole H1 penetrating through the semiconductor substrate 2 and reaching the insulating layer 4 is formed at a position corresponding to a photosensitive region S1. Next, an irregular asperity 22 is formed in a surface 7 of an n+ type embedded layer 6 exposed in the hole H1. The surface of the n+ type embedded layer 6 exposed in the hole H1 through the insulating layer 4 is irradiated with a picosecond to femtosecond pulsed laser beam, whereby the insulating layer 4 is removed and the surface 7 of the n+ type embedded layer 6 exposed in the hole H1 is roughened by the picosecond to femtosecond pulsed laser beam, to form the irregular asperity 22 in the entire area of the surface 7. Then the substrate with the irregular asperity 22 therein is subjected to a thermal treatment.
摘要翻译： 在绝缘层4露出之前对半导体衬底2进行干蚀刻，从而在对应于感光区域S1的位置处形成贯穿半导体衬底2并到达绝缘层4的孔H1。 接下来，在露出在孔H1中的n +型嵌入层6的表面7中形成不规则的凹凸22。 通过绝缘层4暴露在孔H1中的n +型嵌入层6的表面用皮秒照射到飞秒脉冲激光束，由此去除绝缘层4，并将n +型嵌入层6的表面7暴露在 通过皮秒对飞秒脉冲激光束使孔H1粗糙化，在表面7的整个区域中形成不规则的凹凸22。然后对其中具有不规则凹凸22的基板进行热处理。
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公开(公告)号：US20110298076A1
公开(公告)日：2011-12-08
申请号：US13202244
申请日：2010-02-15
IPC分类号： H01L31/0236
CPC分类号： H01L31/02366 , H01L27/1446 , H01L27/1464 , H01L31/0236 , H01L31/02363 , H01L31/028 , H01L31/107 , H01L31/1804 , Y02E10/547
摘要： A p− type semiconductor substrate 20 has a first principal surface 20a and a second principal surface 20b opposed to each other and includes a photosensitive region 21. The photosensitive region 21 is composed of an n+ type impurity region 23, a p+ type impurity region 25, and a region to be depleted with application of a bias voltage in the p− type semiconductor substrate 20. An irregular asperity 10 is formed in the second principal surface 20b of the p− type semiconductor substrate 20. An accumulation layer 37 is formed on the second principal surface 20b side of the p− type semiconductor substrate 20 and a region in the accumulation layer 37 opposed to the photosensitive region 21 is optically exposed.
摘要翻译： p型半导体衬底20具有彼此相对并包括感光区域21的第一主表面20a和第二主表面20b。感光区域21由n +型杂质区域23，p +型杂质区域25 以及在p型半导体衬底20中施加偏置电压而被耗尽的区域。在p型半导体衬底20的第二主表面20b中形成不规则的凹凸10.在 p型半导体衬底20的第二主表面20b侧和与感光区域21相对的累积层37中的区域被光学曝光。
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公开(公告)号：US09190551B2
公开(公告)日：2015-11-17
申请号：US13202244
申请日：2010-02-15
IPC分类号： H01L33/22 , H01L31/107 , H01L27/144 , H01L31/0236 , H01L31/18 , H01L27/146
CPC分类号： H01L31/02366 , H01L27/1446 , H01L27/1464 , H01L31/0236 , H01L31/02363 , H01L31/028 , H01L31/107 , H01L31/1804 , Y02E10/547
摘要： A p− type semiconductor substrate 20 has a first principal surface 20a and a second principal surface 20b opposed to each other and includes a photosensitive region 21. The photosensitive region 21 is composed of an n+ type impurity region 23, a p+ type impurity region 25, and a region to be depleted with application of a bias voltage in the p− type semiconductor substrate 20. An irregular asperity 10 is formed in the second principal surface 20b of the p− type semiconductor substrate 20. An accumulation layer 37 is formed on the second principal surface 20b side of the p− type semiconductor substrate 20 and a region in the accumulation layer 37 opposed to the photosensitive region 21 is optically exposed.
摘要翻译： p型半导体衬底20具有彼此相对并包括感光区域21的第一主表面20a和第二主表面20b。感光区域21由n +型杂质区域23，p +型杂质区域25 以及在p型半导体衬底20中施加偏置电压而被耗尽的区域。在p型半导体衬底20的第二主表面20b中形成不规则的凹凸10.在 p型半导体衬底20的第二主表面20b侧和与感光区域21相对的累积层37中的区域被光学曝光。
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公开(公告)号：US08742528B2
公开(公告)日：2014-06-03
申请号：US13147884
申请日：2010-02-15
IPC分类号： H01L31/0232 , H01L27/146
CPC分类号： H01L27/1464 , H01L27/1462 , H01L27/14625 , H01L27/1463 , H01L27/14649 , H01L27/14689 , H01L31/0232 , H01L31/0236 , H01L31/02363 , H01L31/035281 , H01L31/103 , H01L31/107 , H01L2224/48091 , Y02E10/50 , H01L2924/00014
摘要： A photodiode array PDA1 is provided with a substrate S wherein a plurality of photodetecting channels CH have an n-type semiconductor layer 32. The photodiode array PDA1 is provided with a p− type semiconductor layer 33 formed on the n-type semiconductor layer 32, resistors 24 provided for the respective photodetecting channels CH and each having one end portion connected to a signal conducting wire 23, and an n-type separating portion 40 formed between the plurality of photodetecting channels CH. The p− type semiconductor layer 33 forms pn junctions at an interface to the n-type semiconductor layer 32 and has a plurality of multiplication regions AM for avalanche multiplication of carriers generated with incidence of detection target light, corresponding to the respective photodetecting channels. An irregular asperity 10 is formed in a surface of the n-type semiconductor layer 32 and the surface is optically exposed.
摘要翻译： 光电二极管阵列PDA1设置有基板S，其中多个受光通道CH具有n型半导体层32.光电二极管阵列PDA1设置有形成在n型半导体层32上的p型半导体层33，电阻 设置在相应的光检测通道CH上，每个具有连接到信号导线23的一个端部，以及形成在多个光电检测通道CH之间的n型分离部分40。 p型半导体层33在与n型半导体层32的界面处形成pn结，并且具有多个乘法区域AM，用于对应于各个受光通道而与检测目标光入射产生的载流子的雪崩乘法。 在n型半导体层32的表面上形成不规则的凹凸10，并且该表面被光学曝光。
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公开(公告)号：US20110266644A1
公开(公告)日：2011-11-03
申请号：US13143765
申请日：2010-02-09
申请人： Kazuhisa Yamamura , Akira Sakamoto , Terumasa Nagano , Yasuhito Miyazaki , Yasuhito Yoneta , Hisanori Suzuki , Masaharu Muramatsu
发明人： Kazuhisa Yamamura , Akira Sakamoto , Terumasa Nagano , Yasuhito Miyazaki , Yasuhito Yoneta , Hisanori Suzuki , Masaharu Muramatsu
IPC分类号： H01L31/02
CPC分类号： H01L31/0236 , H01L27/1462 , H01L27/1464 , H01L31/02327 , H01L31/035281 , H01L31/103 , Y02E10/50
摘要： A semiconductor photodetection element SP has a silicon substrate 21 comprised of a semiconductor of a first conductivity type, having a first principal surface 21a and a second principal surface 21b opposed to each other, and having a semiconductor layer 23 of a second conductivity type formed on the first principal surface 21a side; and charge transfer electrodes 25 provided on the first principal surface 21a and adapted to transfer generated charge. In the silicon substrate 21, an accumulation layer 31 of the first conductivity type having a higher impurity concentration than the silicon substrate 21 is formed on the second principal surface 21b side and an irregular asperity 10 is formed in a region opposed to at least the semiconductor region 23, in the second principal surface 21b. The region where the irregular asperity 10 is formed in the second principal surface 21b of the silicon substrate 21 is optically exposed.
摘要翻译： 半导体光检测元件SP具有由第一导电类型的半导体构成的硅基板21，第一导电类型的半导体具有彼此相对的第一主表面21a和第二主表面21b，并且具有第二导电类型的半导体层23形成在 第一主表面21a侧; 以及设置在第一主表面21a上并适于传送产生的电荷的电荷转移电极25。 在硅基板21中，在第二主面21b侧形成有比硅基板21高的杂质浓度的第一导电类型的累积层31，并且在与至少半导体相对的区域中形成不规则的凹凸10 区域23，在第二主表面21b中。 在硅衬底21的第二主表面21b中形成不规则凹凸10的区域被光学曝光。
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公开(公告)号：US08629485B2
公开(公告)日：2014-01-14
申请号：US13143765
申请日：2010-02-09
申请人： Kazuhisa Yamamura , Akira Sakamoto , Terumasa Nagano , Yasuhito Miyazaki , Yasuhito Yoneta , Hisanori Suzuki , Masaharu Muramatsu
发明人： Kazuhisa Yamamura , Akira Sakamoto , Terumasa Nagano , Yasuhito Miyazaki , Yasuhito Yoneta , Hisanori Suzuki , Masaharu Muramatsu
IPC分类号： H01L31/062
CPC分类号： H01L31/0236 , H01L27/1462 , H01L27/1464 , H01L31/02327 , H01L31/035281 , H01L31/103 , Y02E10/50
摘要： A semiconductor photodetection element SP has a silicon substrate 21 comprised of a semiconductor of a first conductivity type, having a first principal surface 21a and a second principal surface 21b opposed to each other, and having a semiconductor layer 23 of a second conductivity type formed on the first principal surface 21a side; and charge transfer electrodes 25 provided on the first principal surface 21a and adapted to transfer generated charge. In the silicon substrate 21, an accumulation layer 31 of the first conductivity type having a higher impurity concentration than the silicon substrate 21 is formed on the second principal surface 21b side and an irregular asperity 10 is formed in a region opposed to at least the semiconductor region 23, in the second principal surface 21b. The region where the irregular asperity 10 is formed in the second principal surface 21b of the silicon substrate 21 is optically exposed.
摘要翻译： 半导体光检测元件SP具有由第一导电类型的半导体构成的硅基板21，第一导电类型的半导体具有彼此相对的第一主表面21a和第二主表面21b，并且具有第二导电类型的半导体层23形成在 第一主表面21a侧; 以及设置在第一主表面21a上并适于传送产生的电荷的电荷转移电极25。 在硅基板21中，在第二主面21b侧形成有比硅基板21高的杂质浓度的第一导电类型的累积层31，并且在与至少半导体相对的区域中形成不规则的凹凸10 区域23，在第二主表面21b中。 在硅衬底21的第二主表面21b中形成不规则凹凸10的区域被光学曝光。
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公开(公告)号：US20110291218A1
公开(公告)日：2011-12-01
申请号：US13147884
申请日：2010-02-15
IPC分类号： H01L27/146 , H01L31/09
CPC分类号： H01L27/1464 , H01L27/1462 , H01L27/14625 , H01L27/1463 , H01L27/14649 , H01L27/14689 , H01L31/0232 , H01L31/0236 , H01L31/02363 , H01L31/035281 , H01L31/103 , H01L31/107 , H01L2224/48091 , Y02E10/50 , H01L2924/00014
摘要： A photodiode array PDA1 is provided with a substrate S wherein a plurality of photodetecting channels CH have an n-type semiconductor layer 32. The photodiode array PDA1 is provided with a p− type semiconductor layer 33 formed on the n-type semiconductor layer 32, resistors 24 provided for the respective photodetecting channels CH and each having one end portion connected to a signal conducting wire 23, and an n-type separating portion 40 formed between the plurality of photodetecting channels CR The p− type semiconductor layer 33 forms pn junctions at an interface to the n-type semiconductor layer 32 and has a plurality of multiplication regions AM for avalanche multiplication of carriers generated with incidence of detection target light, corresponding to the respective photodetecting channels. An irregular asperity 10 is formed in a surface of the n-type semiconductor layer 32 and the surface is optically exposed.
摘要翻译： 光电二极管阵列PDA1设置有基板S，其中多个受光通道CH具有n型半导体层32.光电二极管阵列PDA1设置有形成在n型半导体层32上的p型半导体层33，电阻 设置在相应的光检测通道CH上，并且每个具有连接到信号导线23的一个端部，以及形成在多个光电通道CR之间的n型分离部分40. p型半导体层33形成在p型结 与n型半导体层32接口，并且具有多个乘法区域AM，用于与检测目标光入射产生的载流子的雪崩乘法相对应的各个受光通道。 在n型半导体层32的表面上形成不规则的凹凸10，并且该表面被光学曝光。
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公开(公告)号：US20110291213A1
公开(公告)日：2011-12-01
申请号：US13148091
申请日：2010-02-15
IPC分类号： H01L31/0232 , H01L31/18
CPC分类号： H01L31/1804 , H01L31/02327 , H01L31/02363 , H01L31/035281 , Y02E10/547
摘要： A semiconductor substrate 2 is dry etched before an insulating layer 4 is exposed, whereby a hole H1 penetrating through the semiconductor substrate 2 and reaching the insulating layer 4 is formed at a position corresponding to a photosensitive region S1. Next, an irregular asperity 22 is formed in a surface 7 of an n+ type embedded layer 6 exposed in the hole H1. The surface of the n+ type embedded layer 6 exposed in the hole H1 through the insulating layer 4 is irradiated with a picosecond to femtosecond pulsed laser beam, whereby the insulating layer 4 is removed and the surface 7 of the n+ type embedded layer 6 exposed in the hole H1 is roughened by the picosecond to femtosecond pulsed laser beam, to form the irregular asperity 22 in the entire area of the surface 7. Then the substrate with the irregular asperity 22 therein is subjected to a thermal treatment.
摘要翻译： 在绝缘层4露出之前对半导体衬底2进行干蚀刻，从而在对应于感光区域S1的位置处形成贯穿半导体衬底2并到达绝缘层4的孔H1。 接下来，在露出在孔H1中的n +型嵌入层6的表面7中形成不规则的凹凸22。 通过绝缘层4暴露在孔H1中的n +型嵌入层6的表面用皮秒照射到飞秒脉冲激光束，由此去除绝缘层4，并将n +型嵌入层6的表面7暴露在 通过皮秒对飞秒脉冲激光束使孔H1粗糙化，在表面7的整个区域中形成不规则的凹凸22。然后对其中具有不规则凹凸22的基底进行热处理。
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