公开(公告)号：US5281547A

公开(公告)日：1994-01-25

申请号：US778986

申请日：1991-11-12

申请人： Akira Uchiyama ,  Takahisa Hayashi ,  Toshiyuki Ochiai

发明人： Akira Uchiyama ,  Takahisa Hayashi ,  Toshiyuki Ochiai

IPC分类号： H01L21/336 ,  H01L27/092 ,  H01L29/08 ,  H01L29/423 ,  H01L21/265

CPC分类号： H01L29/785 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/66787

摘要： A field effect transistor of the present invention has in a base layer (33) a difference in levels constituted by an upper main surface (35a) a wall surface (35b) and a lower main surface (35c), the wall surface (35b) having a gate insulating film (39) and a gate electrode (41) in a sequential order at least in a direction extending from the upper main surface (35a) to the lower main surface (35c), the wall surface (35b) being provided, on both sides of the portions thereof corresponding to the gate insulating film (39) and gate electrode (41), with inpurity diffusion regions for forming of source and drain, respectively.Accordingly, the gate electrode (41) is provided in a manner that the gate width which needs to have a relatively large size is set in a direction vertical to the upper main surface of the base layer. This makes it possible to improve the degree of integration effectively.

摘要翻译： PCT No.PCT / JP90 / 00416 Sec。 371日期1991年11月12日 102（e）日期1991年11月12日PCT 1990年3月28日PCT公布。 出版物WO90 / 13918 1990年11月15日，本发明的场效应晶体管在基层（33）中具有由上表面（35a），壁面（35b）和下主表面（35c）构成的水平差， ，至少在从上主表面（35a）到下主表面（35c）延伸的方向上依次具有栅极绝缘膜（39）和栅电极（41）的壁表面（35b）， 在与栅极绝缘膜（39）和栅电极（41）对应的部分的两侧分别设置有用于形成源极和漏极的不纯度扩散区域的壁面（35b）。 因此，栅电极（41）的设置方式是使得需要具有较大尺寸的栅极宽度设定在与基底层的上主表面垂直的方向上。 这样可以有效地提高集成度。

公开(公告)号：US06340973B1

公开(公告)日：2002-01-22

申请号：US09244036

申请日：1999-02-04

申请人： Toshiyuki Ochiai ,  Yosuke Furukawa ,  Yutaka Tanaka ,  Kozo Kimura ,  Makoto Hirai ,  Tokuzo Kiyohara ,  Hideshi Nishida

发明人： Toshiyuki Ochiai ,  Yosuke Furukawa ,  Yutaka Tanaka ,  Kozo Kimura ,  Makoto Hirai ,  Tokuzo Kiyohara ,  Hideshi Nishida

IPC分类号： G06F13372

CPC分类号： G06F13/1647 ,  G11C7/1072 ,  G11C7/22

摘要： A transfer-target unit outputs commands for data reading and data writing. An address generator generates control signals in accordance with the commands, and outputs the number of bytes of data first transferred by read access. A command generator generates control commands in accordance with the control signals to control an SDRAM. At this time the command generator judges the number of transferred bytes to control so that the SDRAM executes instructions in order from an instruction which is the most efficient in data transfer. That is, in the case where data is read across a bank boundary, the command generator judges which is to be executed first between read processing in a bank 0 and active processing in a bank1, to control the SDRAM. A data processor mediates data transfer between the transfer-target unit and the SDRAM in accordance with the control commands. In this way, it is possible to issue commands so as to terminate data transfer in the minimum number of cycles in the case where data read processing is continuously performed to different banks. The number of cycles required for two continuous access (access to the bank 0 and the bank 1) can be thus reduced, thereby increasing effective transfer rates of the SDRAM.

摘要翻译： 传输目标单元输出用于数据读取和数据写入的命令。 地址生成器根据命令生成控制信号，并输出通过读取访问首先传送的数据的字节数。 命令发生器根据控制信号产生控制命令以控制SDRAM。 此时，命令生成器判断要进行控制的传送字节数，使得SDRAM从数据传输中最有效的指令按顺序执行指令。 也就是说，在通过存储体边界读取数据的情况下，命令生成器判断在存储体0中的读取处理和存储体1中的有效处理之间首先执行哪个，以控制SDRAM。 数据处理器根据控制命令介入转移目标单元和SDRAM之间的数据传输。以这种方式，可以发出命令，以便在数据读取的情况下以最小数量的周期终止数据传输 不断对不同的银行进行处理。 因此可以减少两次连续访问（对存储体0和存储体1的访问）所需的周期数，从而增加SDRAM的有效传输速率。

公开(公告)号：US6141729A

公开(公告)日：2000-10-31

申请号：US723872

申请日：1996-09-23

申请人： Hideo Ishida ,  Toshiyuki Ochiai ,  Yutaka Tanaka ,  Teruto Hirota ,  Akihiko Wada ,  Eiichi Toyonaga ,  Kunihiko Sakoda

发明人： Hideo Ishida ,  Toshiyuki Ochiai ,  Yutaka Tanaka ,  Teruto Hirota ,  Akihiko Wada ,  Eiichi Toyonaga ,  Kunihiko Sakoda

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/38 ,  G06F15/173 ,  G06F12/02

CPC分类号： G06F13/387

摘要： A data transfer system comprises a plurality of terminals; a plurality of high-speed data transfer units connected to the terminals through a network, each data transfer unit comprising a plurality of storage devices and a storage device group control device or unit for controlling readout of data from the storage devices, and dividing and storing data requested by the terminals; a virtual storage device group controlling device or unit for controlling readout of data from virtual storage device groups, each virtual storage device group being constructed by selecting a storage device from each high-speed data transfer unit; and an instruction conversion unit or device for receiving a data readout instruction on the basis of data requests output from the terminals, which instruction is given to the virtual storage device groups, from the virtual storage device group control unit or device, and converting the instruction into a data readout instruction to the storage devices from the storage device group control unit or device. In this data transfer system, the load for the data transfer processing is equally distributed among the high-speed data transfer units even when data transfer requests are output from plural terminals.

摘要翻译： 数据传输系统包括多个终端; 通过网络连接到终端的多个高速数据传送单元，每个数据传送单元包括多个存储设备和用于控制来自存储设备的数据读出的存储设备组控制设备或单元，以及分配和存储 终端请求的数据; 虚拟存储设备组控制设备或单元，用于控制来自虚拟存储设备组的数据读取，每个虚拟存储设备组通过从每个高速数据传送单元中选择一个存储设备来构造; 以及指令转换单元或装置，用于基于从虚拟存储设备组控制单元或设备向虚拟存储设备组发送指令，从终端输出的数据请求接收数据读出指令，并将指令转换 从存储设备组控制单元或设备到存储设备的数据读取指令。 在该数据传送系统中，即使当从多个终端输出数据传送请求时，数据传送处理的负载也均匀地分配在高速数据传送单元中。

公开(公告)号：US09166642B2

公开(公告)日：2015-10-20

申请号：US13404343

申请日：2012-02-24

申请人： Toshiyuki Ochiai

发明人： Toshiyuki Ochiai

IPC分类号： H04B1/10 ,  H04B1/28 ,  H04B1/403 ,  H03J1/00 ,  H03J3/08

CPC分类号： H04B1/28 ,  H03J1/0008 ,  H03J3/08 ,  H03J2200/10 ,  H04B1/406 ,  H04B2001/1054

摘要： A signal receiving device and signal receiving method to pass a desired frequency component of an intermediate frequency signal by using an IF filter without increasing a chip area. The signal receiving device comprises: a mixer to mix a received frequency signal with a local oscillation frequency signal to generate an intermediate frequency signal; an IF filter to pass a predetermined frequency component of the intermediate frequency signal; a controlling part which adjusts, according to a frequency band of the intermediate frequency signal, the frequency band of the IF filter, and adjust, according to a center frequency set in the IF filter that fluctuates with the adjustment, a center frequency of the intermediate frequency signal to be inputted in the IF filter; and a demodulating part to demodulate a frequency component of the intermediate frequency signal outputted after passing through the IF filter.

摘要翻译： 一种信号接收装置和信号接收方法，用于在不增加芯片面积的情况下通过使用IF滤波器传递中频信号的期望频率分量。 信号接收装置包括：混频器，用于将接收到的频率信号与本地振荡频率信号混频以产生中频信号; IF滤波器，用于通过中频信号的预定频率分量; 控制部分，根据中频信号的频带调整IF滤波器的频带，并且根据在调整波动的IF滤波器中设置的中心频率来调整中频信号的中间频率 要在IF滤波器中输入频率信号; 以及解调部分，用于解调通过IF滤波器之后输出的中频信号的频率分量。

公开(公告)号：US06509805B2

公开(公告)日：2003-01-21

申请号：US09810663

申请日：2001-03-19

申请人： Toshiyuki Ochiai

发明人： Toshiyuki Ochiai

IPC分类号： H03B508

CPC分类号： H03B5/1228 ,  H03B5/1215 ,  H03B5/1243 ,  H03B5/1265

摘要： A control voltage Vin that has been input is sequentially reduced at NMOS's 111˜113 constituting means for voltage reduction. The individual voltages resulting from the voltage reduction are applied to control electrodes of MOS varactors 211˜213 constituting voltage-controlled variable-capacitance elements which are connected in parallel and, thus, the capacitance values of the individual MOS varactors 211˜213 are determined. An LC resonance circuit constituted of the MOS varactors 211˜213 and a coil 22 resonates at a specific frequency, NMOS's 23 and 24 constituting means for switching engage in on/off operation and oscillation occurs at an oscillation frequency corresponding to the voltage Vin resulting in an oscillation signal output through output terminals 3 and 4. Thus, an LC resonance circuit that allows the rate at which the capacitance values of the voltage-controlled variable-capacitance elements change to be set freely in correspondence to the particulars of design and a high-performance voltage-controlled oscillation circuit (VCO) that employs this LC resonance circuit and enables good control are provided.

公开(公告)号：US5978879A

公开(公告)日：1999-11-02

申请号：US877208

申请日：1997-06-17

申请人： Hideaki Harumoto ,  Toshiyuki Ochiai ,  Taihei Yugawa

发明人： Hideaki Harumoto ,  Toshiyuki Ochiai ,  Taihei Yugawa

IPC分类号： G06F13/36 ,  G06F13/362 ,  G06F13/40 ,  G06F13/00

CPC分类号： G06F13/362 ,  G06F13/4031

摘要： A bus bridge apparatus that connects two system buses independent of each other to which a bus arbiter operating independently and located outside of the apparatus, has a function for serving as a master and a slave of the system buses, a base address holding means, and a bus address generating means. When, to access a slave device on a first system bus, a master device on a second system bus attempts to access the apparatus, generating offset from addresses received from the master device and combining the offset with base addresses previously stored in said base address holding means, to generate an access destination address in the slave device by using said bus address generating means, this bus bridge apparatus performs functions: (i) issuing the generated access destination address by serving as a bus master on the first system bus, to access the slave device; and (ii) performing data transfer between the master device and the slave device by serving as a slave of the master device on the second system bus. It is thus possible to realize mutual access between system buses having an independent arbitration function, without changing system design.

摘要翻译： 连接两个独立于总线仲裁器的系统总线的总线桥接装置，其独立地位于设备外部，具有用作系统总线的主机和从机的功能，基地址保持装置和 总线地址产生装置。 当要访问第一系统总线上的从设备时，第二系统总线上的主设备尝试访问设备，从主设备接收的地址产生偏移量，并将偏移与先前存储在所述基地址保持中的基地址组合 意味着通过使用所述总线地址产生装置在从设备中生成接入目的地地址，该总线桥接装置执行以下功能：（i）通过在第一系统总线上作为总线主机发送生成的接入目的地地址，以访问 从设备; 以及（ii）通过在第二系统总线上作为主设备的从设备在主设备和从设备之间执行数据传输。 因此，可以在不改变系统设计的情况下实现具有独立仲裁功能的系统总线之间的相互访问。

公开(公告)号：US5579500A

公开(公告)日：1996-11-26

申请号：US200217

申请日：1994-02-23

申请人： Tsutomu Sekibe ,  Tomohiko Kitamura ,  Toshiyuki Ochiai

发明人： Tsutomu Sekibe ,  Tomohiko Kitamura ,  Toshiyuki Ochiai

IPC分类号： G06F12/02

CPC分类号： G06F12/0215

摘要： An apparatus and method for controlling data read access to memory, in response to an access request sent through a system bus. The apparatus includes an data storage device for preserving data corresponding to a predetermined address; a judging device for judging whether an access address indicated by the access request matches the predetermined address; and a control device for making the data storage device output data preserved therein to the system bus when the access address has been judged to match the predetermined address, and for making the data storage device hold data corresponding to a next address subsequent to the access address when the access address has been judged not to match the predetermined address.

摘要翻译： 响应于通过系统总线发送的访问请求，控制对存储器的数据读取访问的装置和方法。 该装置包括用于保存对应于预定地址的数据的数据存储装置; 用于判断由所述访问请求指示的访问地址是否匹配所述预定地址的判断装置; 以及控制装置，用于当访问地址已经被判定为与预定地址相匹配时，用于使数据存储装置输出保存在其中的数据到系统总线，并且使得数据存储装置保持对应于访问地址之后的下一个地址的数据 当访问地址被判定为不符合预定地址时。