公开(公告)号：US6141729A

公开(公告)日：2000-10-31

申请号：US723872

申请日：1996-09-23

申请人： Hideo Ishida ,  Toshiyuki Ochiai ,  Yutaka Tanaka ,  Teruto Hirota ,  Akihiko Wada ,  Eiichi Toyonaga ,  Kunihiko Sakoda

发明人： Hideo Ishida ,  Toshiyuki Ochiai ,  Yutaka Tanaka ,  Teruto Hirota ,  Akihiko Wada ,  Eiichi Toyonaga ,  Kunihiko Sakoda

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/38 ,  G06F15/173 ,  G06F12/02

CPC分类号： G06F13/387

摘要： A data transfer system comprises a plurality of terminals; a plurality of high-speed data transfer units connected to the terminals through a network, each data transfer unit comprising a plurality of storage devices and a storage device group control device or unit for controlling readout of data from the storage devices, and dividing and storing data requested by the terminals; a virtual storage device group controlling device or unit for controlling readout of data from virtual storage device groups, each virtual storage device group being constructed by selecting a storage device from each high-speed data transfer unit; and an instruction conversion unit or device for receiving a data readout instruction on the basis of data requests output from the terminals, which instruction is given to the virtual storage device groups, from the virtual storage device group control unit or device, and converting the instruction into a data readout instruction to the storage devices from the storage device group control unit or device. In this data transfer system, the load for the data transfer processing is equally distributed among the high-speed data transfer units even when data transfer requests are output from plural terminals.

摘要翻译： 数据传输系统包括多个终端; 通过网络连接到终端的多个高速数据传送单元，每个数据传送单元包括多个存储设备和用于控制来自存储设备的数据读出的存储设备组控制设备或单元，以及分配和存储 终端请求的数据; 虚拟存储设备组控制设备或单元，用于控制来自虚拟存储设备组的数据读取，每个虚拟存储设备组通过从每个高速数据传送单元中选择一个存储设备来构造; 以及指令转换单元或装置，用于基于从虚拟存储设备组控制单元或设备向虚拟存储设备组发送指令，从终端输出的数据请求接收数据读出指令，并将指令转换 从存储设备组控制单元或设备到存储设备的数据读取指令。 在该数据传送系统中，即使当从多个终端输出数据传送请求时，数据传送处理的负载也均匀地分配在高速数据传送单元中。

公开(公告)号：US06340973B1

公开(公告)日：2002-01-22

申请号：US09244036

申请日：1999-02-04

申请人： Toshiyuki Ochiai ,  Yosuke Furukawa ,  Yutaka Tanaka ,  Kozo Kimura ,  Makoto Hirai ,  Tokuzo Kiyohara ,  Hideshi Nishida

发明人： Toshiyuki Ochiai ,  Yosuke Furukawa ,  Yutaka Tanaka ,  Kozo Kimura ,  Makoto Hirai ,  Tokuzo Kiyohara ,  Hideshi Nishida

IPC分类号： G06F13372

CPC分类号： G06F13/1647 ,  G11C7/1072 ,  G11C7/22

摘要： A transfer-target unit outputs commands for data reading and data writing. An address generator generates control signals in accordance with the commands, and outputs the number of bytes of data first transferred by read access. A command generator generates control commands in accordance with the control signals to control an SDRAM. At this time the command generator judges the number of transferred bytes to control so that the SDRAM executes instructions in order from an instruction which is the most efficient in data transfer. That is, in the case where data is read across a bank boundary, the command generator judges which is to be executed first between read processing in a bank 0 and active processing in a bank1, to control the SDRAM. A data processor mediates data transfer between the transfer-target unit and the SDRAM in accordance with the control commands. In this way, it is possible to issue commands so as to terminate data transfer in the minimum number of cycles in the case where data read processing is continuously performed to different banks. The number of cycles required for two continuous access (access to the bank 0 and the bank 1) can be thus reduced, thereby increasing effective transfer rates of the SDRAM.

摘要翻译： 传输目标单元输出用于数据读取和数据写入的命令。 地址生成器根据命令生成控制信号，并输出通过读取访问首先传送的数据的字节数。 命令发生器根据控制信号产生控制命令以控制SDRAM。 此时，命令生成器判断要进行控制的传送字节数，使得SDRAM从数据传输中最有效的指令按顺序执行指令。 也就是说，在通过存储体边界读取数据的情况下，命令生成器判断在存储体0中的读取处理和存储体1中的有效处理之间首先执行哪个，以控制SDRAM。 数据处理器根据控制命令介入转移目标单元和SDRAM之间的数据传输。以这种方式，可以发出命令，以便在数据读取的情况下以最小数量的周期终止数据传输 不断对不同的银行进行处理。 因此可以减少两次连续访问（对存储体0和存储体1的访问）所需的周期数，从而增加SDRAM的有效传输速率。

公开(公告)号：US06070201A

公开(公告)日：2000-05-30

申请号：US937798

申请日：1997-09-25

申请人： Yutaka Tanaka ,  Keiji Okamoto ,  Hideo Ishida

发明人： Yutaka Tanaka ,  Keiji Okamoto ,  Hideo Ishida

IPC分类号： G06F3/06 ,  G06F13/368

CPC分类号： G06F3/0626 ,  G06F3/0656 ,  G06F3/0689

摘要： A memory control device having a plurality of data transfer paths including a storage device group comprising a plurality of storage devices for storing data and a buffer memory group comprising multiple buffer memories for storing transferred data, dividing files into multiple blocks for storing blocks in multiple storage devices on different data transfer paths, and executing control to read data from the storage device to be output with a request from a connected terminal to the buffer memory wherein storage devices on different paths create multiple virtual storage device groups, and buffer memories create virtual buffer memory groups. The memory control device comprises a data output control for executing control in a first cycle, the data being temporarily dividedly stored in a prescribed virtual storage device group. In a second cycle the device outputs data stored in the virtual buffer memory group and by alternately repeating first and second cycles, data read from the plural virtual buffer memories group is switched.

摘要翻译： 一种具有多个数据传输路径的存储器控​​制装置，包括包括用于存储数据的多个存储装置的存储装置组和包括用于存储传送数据的多个缓冲存储器的缓冲存储器组，将文件划分成用于存储多个存储块的多个块 设备在不同的数据传输路径上，并且执行控制以从存储设备读取数据，以便从连接的终端到缓冲存储器的请求输出，其中不同路径上的存储设备创建多个虚拟存储设备组，并且缓冲存储器创建虚拟缓冲器 记忆组。 存储器控制装置包括用于在第一周期中执行控制的数据输出控制，数据被暂时地分割存储在规定的虚拟存储装置组中。 在第二周期中，设备输出存储在虚拟缓冲存储器组中的数据，并且通过交替重复第一和第二周期，切换从多个虚拟缓冲存储器组读取的数据。

公开(公告)号：US6029189A

公开(公告)日：2000-02-22

申请号：US986785

申请日：1997-12-08

申请人： Hideo Ishida ,  Yutaka Tanaka

发明人： Hideo Ishida ,  Yutaka Tanaka

IPC分类号： G06F3/06 ,  H04N7/173 ,  G06F13/00

CPC分类号： G06F3/061 ,  G06F3/0635 ,  G06F3/0689 ,  H04N7/17336

摘要： In a data transfer system in which when a first to fourth terminals require reading data, the data are read out of a first to fourth storages to be stored in a first and second buffer memories while a first and second virtual groups of storages are alternately switched every constant cycle, and thereafter a first and second data sending units send the data stored in the first and second buffer memories to the terminals; on the other hand, when the first to fourth terminals require writing data, received data is divided in a way to distribute the process loads of data read and data write of the divided data equally into a first and second data transfer units. At the same time, the data are stored in the first and second buffer memories of the first and second data transfer units, and thereafter the data are written into the first to fourth storages while switching the first and second virtual groups of storages alternately. As a result, the load of transferring data to the terminals is not concentrated on a particular data transfer unit in the data transfer system, even when the rate of request-to-reads from the terminals changes or differs from those of others.

摘要翻译： 在第一至第四终端需要读取数据的数据传输系统中，从第一至第四存储器中读出数据以存储在第一和第二缓冲存储器中，同时第一和第二虚拟存储组交替地切换 每个恒定周期，然后第一和第二数据发送单元将存储在第一和第二缓冲存储器中的数据发送到终端; 另一方面，当第一至第四终端需要写入数据时，以将分割数据的数据读取和数据写入的处理负载均等地分配到第一和第二数据传送单元的方式分割接收数据。 同时，将数据存储在第一和第二数据传送单元的第一和第二缓冲存储器中，然后数据被写入第一至第四存储器，同时交替地切换第一和第二虚拟存储组。 结果，即使当从终端请求读取的速率变化或与其他的不同时，向终端传送数据的负载也不集中在数据传送系统中的特定数据传送单元上。

公开(公告)号：US20140096733A1

公开(公告)日：2014-04-10

申请号：US14118918

申请日：2012-05-14

申请人： Tomohiro Nakamura ,  Yutaka Tanaka ,  Yoshihito Fujishiro ,  Yasuo Toyoshima

发明人： Tomohiro Nakamura ,  Yutaka Tanaka ,  Yoshihito Fujishiro ,  Yasuo Toyoshima

IPC分类号： F02P19/02

CPC分类号： F02P19/02 ,  F02D41/266 ,  F02D2041/2058 ,  F02P19/027 ,  F23Q7/001

摘要： There is provided a new glow plug that can be easily determined as to whether or not it is a new article.An additional circuit 12 formed by connecting a diode 13, a fuse 14, and an adjusting resistor 15 in series in this order is connected in parallel to a heating element 11 of a glow plug 1. The diode 13 is provided so as to have an anode located on the positive electrode side of the heating element 11 and a cathode located on the fuse 14 side. In the case of a unit inspection, by applying a positive voltage for test to a heating element negative electrode connecting portion 3a, it is possible to determine whether or not the glow plug 1 is normal without blowing the fuse 14 before the glow plug 1 is used in a vehicle.

摘要翻译： 提供了一个新的电热塞，可以很容易地确定它是否是一个新的文章。 依次连接二极管13，熔断器14和调节电阻器15而构成的附加电路12与电热塞1的加热元件11并联连接。二极管13设置成具有 位于加热元件11的正极侧的阳极和位于保险丝14侧的阴极。 在单元检查的情况下，通过向加热元件负极连接部3a施加正电压进行测试，可以在电热塞1为止之前先吹出保险丝14来判断电热塞1是否正常 用于车辆。

公开(公告)号：US20130255615A1

公开(公告)日：2013-10-03

申请号：US13993165

申请日：2011-12-06

申请人： Yoshito Hujishiro ,  Yutaka Tanaka ,  Tomohiro Nakamura

发明人： Yoshito Hujishiro ,  Yutaka Tanaka ,  Tomohiro Nakamura

IPC分类号： F02P23/00

CPC分类号： F02P23/00 ,  F02D2041/2027 ,  F02P19/02 ,  F02P19/022 ,  F02P19/023 ,  F02P19/026 ,  F23Q7/001

摘要： To suppress current fluctuations upon commencement of driving and prolong lifespan by reducing electric stress caused by current fluctuations.A glow plug 1, a glow switch 2, and a stabilizing coil 3 are series-connected, and upon commencement of the driving of the glow plug 1, a repetition frequency of PWM signals that control the opening and closing of the glow switch 2 is made into a higher frequency than a repetition frequency in a normal drive state and the opening and closing of the glow switch 2 is controlled (S104), and when a predetermined drive shift condition has been met (S106), the repetition frequency of the PWM signals is returned to the frequency during normal driving and the opening and closing of the glow switch 2 is controlled (S108), whereby the current upon commencement of driving is smoothed and the occurrence of an instantaneous large current is suppressed.

摘要翻译： 为了抑制驱动开始时的电流波动，通过减少由电流波动引起的电应力来延长寿命。 电热塞1，辉光开关2和稳定线圈3是串联的，并且在电热塞1的驱动开始时，控制辉光开关2的打开和关闭的PWM信号的重复频率是 在正常驱动状态下被制成比重复频率高的频率，并且控制辉光开关2的打开和关闭（S104），并且当满足预定的驱动移位条件（S106）时，PWM的重复频率 信号在正常驱动期间返回到频率，并且控制辉光开关2的打开和关闭（S108），从而驱动开始时的电流平滑，并且抑制了瞬时大电流的发生。

公开(公告)号：US08159852B2

公开(公告)日：2012-04-17

申请号：US12398839

申请日：2009-03-05

申请人： Toshiyuki Kouchi ,  Yutaka Tanaka

发明人： Toshiyuki Kouchi ,  Yutaka Tanaka

IPC分类号： G11C5/02

CPC分类号： G11C8/16 ,  G11C11/412

摘要： A semiconductor memory device includes first and second driving transistors; first and second load transistors; and first and second transmission transistors. Their respective drain diffusion layers of the transistors are isolated from one another. The semiconductor memory device also includes a bit cell in which the first and second driving transistors, the first and second load transistors, and the first and second transmission transistors are arranged; a first wiring for connecting their respective drains of the first driving transistor, the first load transistor, and the first transmission transistor; and a second wiring for connecting their respective drains of the second driving transistor, the second load transistor, and the second transmission transistor.

摘要翻译： 半导体存储器件包括第一和第二驱动晶体管; 第一和第二负载晶体管; 以及第一和第二传输晶体管。 它们各自的漏极扩散层彼此隔离。 半导体存储器件还包括其中布置第一和第二驱动晶体管，第一和第二负载晶体管以及第一和第二传输晶体管的位单元; 用于连接第一驱动晶体管，第一负载晶体管和第一透射晶体管的各自的漏极的第一布线; 以及用于连接其第二驱动晶体管，第二负载晶体管和第二传输晶体管的各自的漏极的第二布线。

公开(公告)号：US20090268499A1

公开(公告)日：2009-10-29

申请号：US12398839

申请日：2009-03-05

申请人： Toshiyuki Kouchi ,  Yutaka Tanaka

发明人： Toshiyuki Kouchi ,  Yutaka Tanaka

IPC分类号： G11C5/02 ,  G11C5/06 ,  G11C8/16

CPC分类号： G11C8/16 ,  G11C11/412

摘要： A semiconductor memory device includes first and second driving transistors; first and second load transistors; and first and second transmission transistors. Their respective drain diffusion layers of the transistors are isolated from one another. The semiconductor memory device also includes a bit cell in which the first and second driving transistors, the first and second load transistors, and the first and second transmission transistors are arranged; a first wiring for connecting their respective drains of the first driving transistor, the first load transistor, and the first transmission transistor; and a second wiring for connecting their respective drains of the second driving transistor, the second load transistor, and the second transmission transistor.

摘要翻译： 半导体存储器件包括第一和第二驱动晶体管; 第一和第二负载晶体管; 以及第一和第二传输晶体管。 它们各自的漏极扩散层彼此隔离。 半导体存储器件还包括其中布置第一和第二驱动晶体管，第一和第二负载晶体管以及第一和第二传输晶体管的位单元; 用于连接第一驱动晶体管，第一负载晶体管和第一透射晶体管的各自的漏极的第一布线; 以及用于连接其第二驱动晶体管，第二负载晶体管和第二传输晶体管的各自的漏极的第二布线。

公开(公告)号：US07566422B2

公开(公告)日：2009-07-28

申请号：US11201142

申请日：2005-08-11

申请人： Shinichi Hara ,  Yutaka Tanaka ,  Shigeru Terashima ,  Takayuki Hasegawa ,  Shin Matsui

发明人： Shinichi Hara ,  Yutaka Tanaka ,  Shigeru Terashima ,  Takayuki Hasegawa ,  Shin Matsui

IPC分类号： G05D16/00 ,  C23C14/00

CPC分类号： G05D16/2013

摘要： A processing apparatus includes a sealed vacuum chamber which contains a processing portion; a pressure controlling system which keeps the internal pressure of the sealed vacuum chamber constant at a predetermined level by exhausting the ambient gas in the sealed vacuum chamber; and an ambient gas recirculating system which recirculates the ambient gas exhausted from the sealed vacuum chamber back into the sealed vacuum chamber; wherein the ambient as recirculated by the ambient gas recirculating system is blown into the sealed vacuum chamber so that a gas flow is generated in a predetermined direction along the processing portion.

摘要翻译： 一种处理装置，包括：密封真空室，其包含处理部分; 压力控制系统，通过排出密封真空室中的环境气体来保持密封真空室的内部压力恒定在预定水平; 以及环境气体循环系统，其将从密封的真空室排出的环境气体再循环回密封的真空室中; 其中由环境气体再循环系统再循环的环境被吹入密封的真空室中，使得沿着处理部分沿预定方向产生气流。

公开(公告)号：US07027718B1

公开(公告)日：2006-04-11

申请号：US09434161

申请日：1999-11-04

申请人： Takeo Ohishi ,  Tsuyoshi Suzuki ,  Yasuaki Yamada ,  Tomoyuki Shindo ,  Yutaka Tanaka

发明人： Takeo Ohishi ,  Tsuyoshi Suzuki ,  Yasuaki Yamada ,  Tomoyuki Shindo ,  Yutaka Tanaka

IPC分类号： H04N5/92 ,  G11B5/00

CPC分类号： H04N21/434 ,  G11B5/0086 ,  G11B5/00878 ,  G11B5/09 ,  G11B15/087 ,  G11B15/125 ,  G11B15/1875 ,  G11B15/4671 ,  G11B15/4731 ,  G11B20/10 ,  G11B20/1208 ,  G11B20/14 ,  G11B27/032 ,  G11B27/10 ,  G11B27/107 ,  G11B27/3036 ,  G11B2020/10592 ,  G11B2220/90 ,  H04L7/0331 ,  H04N5/4401 ,  H04N5/78263 ,  H04N9/7921 ,  H04N9/7973 ,  H04N9/8042

摘要： A packet recording/reproducing system is provided which records or reproduces packets on or from tracks formed in time sequence on a magnetic tape. In a recording operation, the packet recording/reproducing system adds to input packets time stamps whose values are synchronous with packet arrival time control clocks produced by the system. The timing with which the packets are recorded on the magnetic tape is controlled by the arrival time control clocks so that a given number of the packets inputted at high data rate are recorded within a one-track area, a two-track area, or a one-track over area defined across at least two of the tracks, thereby minimizing the loss of capacity of the magnetic tape.

摘要翻译： 提供了一种分组记录/再现系统，其在磁带上以时间顺序形成的轨道上记录或再现分组。 在记录操作中，分组记录/再现系统将与系统产生的分组到达时间控制时钟的值同步的输入分组时间戳添加。 数据包记录在磁带上的时间由到达时间控制时钟控制，使得以高数据速率输入的给定数量的数据包被记录在单磁道区域，双磁道区域或 跨越至少两个轨道限定的单轨道区域，从而最小化磁带的容量损失。