Non-volatile memory and method with block management system
    1.
    发明授权
    Non-volatile memory and method with block management system 有权
    非易失性存储器和方法与块管理系统

    公开(公告)号:US07139864B2

    公开(公告)日:2006-11-21

    申请号:US10750155

    申请日:2003-12-30

    IPC分类号: G06F12/00

    摘要: A non-volatile memory system is organized in physical groups of physical memory locations. Each physical group (metablock) is erasable as a unit and can be used to store a logical group of data. A memory management system allows for update of a logical group of data by allocating a metablock dedicated to recording the update data of the logical group. The update metablock records update data in the order received and has no restriction on whether the recording is in the correct logical order as originally stored (sequential) or not (chaotic). Eventually the update metablock is closed to further recording. One of several processes will take place, but will ultimately end up with a fully filled metablock in the correct order which replaces the original metablock. In the chaotic case, directory data is maintained in the non-volatile memory in a manner that is conducive to frequent updates. The system supports multiple logical groups being updated concurrently.

    摘要翻译: 非易失性存储器系统被组织在物理存储器位置的物理组中。 每个物理组(元区块)作为一个单元是可擦除的,可用于存储一组逻辑数据。 存储器管理系统允许通过分配专用于记录逻辑组的更新数据的元区块来更新逻辑数据组。 更新元区块以所接收的顺序记录更新数据,并且对于是否按照原始存储(顺序)或不是混乱的顺序,记录是否处于正确的逻辑顺序中是没有限制的。 最终,更新元区块被关闭以进一步录制。 几个进程之一将发生,但最终将以完全填充的元区块以正确的顺序取代原来的元区块。 在混乱的情况下,目录数据以有利于频繁更新的方式保存在非易失性存储器中。 系统支持同时更新的多个逻辑组。

    Non-volatile memory control
    2.
    发明申请
    Non-volatile memory control 有权
    非易失性存储器控制

    公开(公告)号:US20070274150A1

    公开(公告)日:2007-11-29

    申请号:US11800974

    申请日:2007-05-08

    申请人: Sergey Gorobets

    发明人: Sergey Gorobets

    IPC分类号: G11C8/12

    摘要: Methods and apparatus for use in a memory system having a non-volatile memory and a controller for limiting the number of non-volatile memory arrays from a plurality of available arrays accessed at one time are useful in the control of concurrent access of memory arrays. One method includes implementing a pipelining sequence for transferring data to and from the non-volatile memory arrays and limiting the number of active arrays operating at one time. The controller is configured to wait for the at least one of the arrays to complete before initiating a transfer to and from a further array.

    摘要翻译: 在具有非易失性存储器的存储器系统中使用的方法和装置以及用于从一次访问的多个可用阵列限制非易失性存储器阵列的数量的控制器在对存储器阵列的并发访问的控制中是有用的。 一种方法包括实现用于将数据传送到非易失性存储器阵列和从非易失性存储器阵列传送数据的流水线序列,并限制一次操作的有源阵列的数量。 控制器被配置为等待至少一个数组完成,然后开始向另一阵列传送数据。

    Dual mode access for non-volatile storage devices
    3.
    发明申请
    Dual mode access for non-volatile storage devices 有权
    非易失性存储设备的双模式访问

    公开(公告)号:US20070143571A1

    公开(公告)日:2007-06-21

    申请号:US11314842

    申请日:2005-12-21

    IPC分类号: G06F12/00

    摘要: Method and mass storage memory system is provided. The system includes, re-programmable non-volatile memory cells, the memory cells being arranged in a plurality of blocks that are erasable together; and a controller including a microprocessor that is adapted to receive files of data identified by unique identifiers via a first interface and the controller causes a received data file to be stored in one or more memory blocks; and the controller receives data identified by logical addresses via a second interface and stores the received data in one or more memory blocks, wherein data written via the first interface is indexed using the unique identifiers so that data is accessible via the second interface or the first interface; and data received via the second interface is indexed so that data can be accessed via the first interface or the second interface.

    摘要翻译: 提供了方法和大容量存储存储系统。 该系统包括可重新编程的非易失性存储器单元,存储单元布置在可以一起可擦除的多个块中; 以及控制器,其包括适于经由第一接口接收由唯一标识符标识的数据的文件的微处理器,并且所述控制器使接收到的数据文件存储在一个或多个存储器块中; 并且控制器经由第二接口接收由逻辑地址识别的数据,并将接收到的数据存储在一个或多个存储器块中,其中经由第一接口写入的数据使用唯一标识符进行索引,使得经由第二接口或第一接口 接口; 并且通过第二接口接收的数据被索引,使得可以经由第一接口或第二接口访问数据。

    Methods for data alignment in non-volatile memories with a directly mapped file storage system
    4.
    发明申请
    Methods for data alignment in non-volatile memories with a directly mapped file storage system 审中-公开
    使用直接映射的文件存储系统在非易失性存储器中进行数据对齐的方法

    公开(公告)号:US20070143567A1

    公开(公告)日:2007-06-21

    申请号:US11316261

    申请日:2005-12-21

    申请人: Sergey Gorobets

    发明人: Sergey Gorobets

    IPC分类号: G06F12/00

    摘要: In the file storage system, each portion belonging to a data file is identified by its file ID and an offset along the data file, where the offset is a constant for the file and every file data portion is always kept at the same position within a memory page to be read or programmed in parallel. In this way, every time a page containing a file portion is read and copy to another page, the data in it is always page-aligned, and each bit within the file portion can always be manipulated by the same sense amplifier and same set data latches within the same memory column. In a preferred implementation, the page alignment is such that (offset within a page)=(data offset within a file) MOD (page size). Any gaps that may exist in page can be padded with any existing page-aligned valid data.

    摘要翻译: 在文件存储系统中,属于数据文件的每个部分由其文件ID和沿着数据文件的偏移来标识,其中偏移量是文件的常数,并且每个文件数据部分总是保持在一个 存储器页面被并行读取或编程。 以这种方式,每次包含文件部分的页面被读取并复制到另一个页面时,其中的数据总是页面对齐的,并且文件部分中的每一位可以总是由相同的读出放大器和相同的设置数据 锁存在同一个内存列中。 在优选实现中,页面对齐使得(页面内的偏移量)=(文件内的数据偏移量)MOD(页面大小)。 页面中可能存在的任何间隙可以用任何现有的页面对齐的有效数据进行填充。

    Pipelined Programming of Non-Volatile Memories Using Early Data
    5.
    发明申请
    Pipelined Programming of Non-Volatile Memories Using Early Data 有权
    使用早期数据的非易失性存储器的流水线编程

    公开(公告)号:US20070014153A1

    公开(公告)日:2007-01-18

    申请号:US11462946

    申请日:2006-08-07

    IPC分类号: G11C16/04

    摘要: The present invention presents techniques whereby a memory system interrupts a programming process and restarts it including additional data. More specifically, when a memory system programs data into a group of cells together as programming unit, programming can begin with less than the full data content which the group can hold. In one embodiment, the present invention allows overlapped programming of upper and lower data pages, where once the memory begins programming the lower logical data page, if data is received for the upper page assigned to the same physical page, programming is interrupted and recommenced with the concurrent programming of both the upper and the loser pages. In a complimentary embodiment, when a page contains multiple sectors of data, programming of the physical page can begin when one or more, but less than all, of the sectors forming the corresponding logical page have been received, stopped and restarted to include additional sectors of the page.

    摘要翻译: 本发明提出了一种存储系统中断编程过程并重新开始包括附加数据的技术。 更具体地说,当存储器系统将数据作为编程单元一起编程成一组单元时,编程可以以少于组可以保存的完整数据内容开始。 在一个实施例中,本发明允许上和下数据页的重叠编程,其中一旦存储器开始编程下逻辑数据页,如果为分配给同一物理页的上页接收到数据,则编程被中断并且以 上下文页面的并发编程。 在一个补充实施例中,当页面包含多个数据扇区时,物理页面的编程可以在形成相应逻辑页面的扇区的一个或多个但是少于所有扇区已被接收,停止并重新启动以包括附加扇区 的页面。

    Non-volatile memory and method with improved indexing for scratch pad and update blocks
    6.
    发明申请
    Non-volatile memory and method with improved indexing for scratch pad and update blocks 有权
    非易失性存储器和方法,改进了临时数据库和更新块的索引

    公开(公告)号:US20060155922A1

    公开(公告)日:2006-07-13

    申请号:US11192386

    申请日:2005-07-27

    IPC分类号: G06F12/00

    CPC分类号: G06F12/0246 G06F2212/7203

    摘要: Update data to a non-volatile memory may be recorded in at least two interleaving streams such as either into an update block or a scratch pad block depending on a predetermined condition. The scratch pad block is used to buffered update data that are ultimately destined for the update block. In a preferred embodiment, an index of the data stored in the scratch pad block as well that stored in the update block is saved in an unused portion of the scratch pad block every time the scratch pad block is written to.

    摘要翻译: 根据预定条件,将数据更新到非易失性存储器可以被记录在至少两个交织流中,诸如更新块或便笺块块中。 缓冲块块用于缓冲最终发往更新块的更新数据。 在优选实施例中,存储在便签区块中的数据的索引以及存储在更新块中的数据被保存在每次写入便笺块块时的便笺本块的未使用部分中。

    Non-volatile memory control
    7.
    发明申请
    Non-volatile memory control 有权
    非易失性存储器控制

    公开(公告)号:US20050018527A1

    公开(公告)日:2005-01-27

    申请号:US10867800

    申请日:2004-06-14

    申请人: Sergey Gorobets

    发明人: Sergey Gorobets

    摘要: According to an embodiment of the present invention, there is provided a method and apparatus for use in a memory system having a non-volatile memory and a controller for limiting the number of non-volatile memory arrays from a plurality of available arrays accessed at one time, wherein the method comprises implementing a pipelining sequence for transferring data to and from the non-volatile memory arrays and limiting the number of active arrays operating at one time, the arrangement being such that the controller waits for the at least one of the arrays to complete before initiating the transfer to and from a further array.

    摘要翻译: 根据本发明的实施例,提供了一种用于具有非易失性存储器的存储器系统中的方法和装置,以及用于从一个存储的多个可用阵列限制非易失性存储器阵列的数量的控制器 时间,其中所述方法包括实现用于将数据传送到非易失性存储器阵列和从所述非易失性存储器阵列传送数据并限制一次操作的有效阵列的数量的流水线序列,所述布置使得所述控制器等待所述阵列中的所述至少一个阵列 在开始转移到另一个数组之前完成。

    Methods for the management of erase operations in non-volatile memories
    8.
    发明申请
    Methods for the management of erase operations in non-volatile memories 有权
    用于管理非易失性存储器中的擦除操作的方法

    公开(公告)号:US20070113030A1

    公开(公告)日:2007-05-17

    申请号:US11273774

    申请日:2005-11-14

    IPC分类号: G06F13/00 G06F12/00

    摘要: The present invention presents a number of improvements for managing erase processes in non-volatile memory. Such memory systems typically manage the memory by logically organize the basic unit of physical erase (erase block) into composite logical groupings (meta-blocks or logical group), where an erase block generally consists of a number of sectors. When an erase command is received, the specified sectors are checked against the memory system's control data. If the specified sectors span any full logical grouping, the full logical groupings can each be treated a whole and erased according to one process (such as performing a true, physical erase), while other sectors are “logically” erased at the sector level by standard techniques.

    摘要翻译: 本发明提出了用于管理非易失性存储器中的擦除处理的许多改进。 这样的存储器系统通常通过将物理擦除的基本单元(擦除块)逻辑地组织到复合逻辑分组(元块或逻辑组)中来管理存储器,其中擦除块通常由多个扇区组成。 当接收到擦除命令时,根据存储器系统的控制数据检查指定的扇区。 如果指定的扇区跨越任何完整的逻辑分组,则可以根据一个进程(例如执行真实的物理擦除)将完整的逻辑分组视为整体并被擦除,而其他扇区在扇区级别被“逻辑”地擦除 标准技术。

    Non-volatile memory with adaptive handling of data writes
    9.
    发明申请
    Non-volatile memory with adaptive handling of data writes 有权
    具有自适应处理数据写入功能的非易失性存储器

    公开(公告)号:US20070101096A1

    公开(公告)日:2007-05-03

    申请号:US11261150

    申请日:2005-10-27

    申请人: Sergey Gorobets

    发明人: Sergey Gorobets

    IPC分类号: G06F12/00 G06F13/00

    摘要: A memory system is presented where sectors are normally stored in logically contiguous groups. As repeated writes of the same small sector group can causes a massive garbage collection (data relocation), the pattern of host access is monitored by checking the sectors' update history and control data structures' update history. When repeated access patterns are detected and then expected again, the “hot” segments are separated into specially handled, non-standard zone in the memory. The non-standard zone has a sector management that is different from the logical groups and optimized for the repeated host accesses in order to reduce the frequency and amount of garbage collection operations.

    摘要翻译: 存在系统,其中扇区通常存储在逻辑上连续的组中。 由于同一小部门组的重复写入可能导致大规模垃圾回收(数据重定位),通过检查扇区的更新历史和控制数据结构的更新历史来监控主机访问模式。 当检测到重复的访问模式,然后再次预期时,“热”段被分成存储器中特别处理的非标准区域。 非标准区域具有与逻辑组不同的扇区管理,并针对重复的主机访问进行了优化,以减少垃圾收集操作的频率和数量。

    On-chip data grouping and alignment

    公开(公告)号:US20060149890A1

    公开(公告)日:2006-07-06

    申请号:US11026549

    申请日:2004-12-30

    申请人: Sergey Gorobets

    发明人: Sergey Gorobets

    IPC分类号: G06F12/00

    摘要: The invention describes the method for regrouping data read from multi-sector pages inside a memory chip. As a result, garbage collection operation time greatly reduces and overall system performance increases. Architectural features include the ability to selectively transfer individual data sectors of a page between on-chip registers and the ability to realign data sectors within a register.