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1.发明授权Algorithmically programmable memory tester with breakpoint trigger, error jamming and 'scope mode that memorizes target sequences 有权具有断点触发，误差干扰和存储目标序列的示波器模式的算法可编程存储器测试仪公开(公告)号：US06834364B2
公开(公告)日：2004-12-21
申请号：US09838766
申请日：2001-04-19
IPC分类号： G06F11273
CPC分类号： G11C29/56
摘要： A trigger signal for a memory tester uses a (breakpoint) trigger qualified according to what part of the test program is being executed. The qualified breakpoint trigger can be delayed before becoming a system trigger signal that can be used to trigger a ‘scope mode and to force an error flag to a selected value so as to compel a particular path with the test program. To provide stable waveforms for the sweeping of the voltage thresholds and sample timing offset the memory tester records the addresses for a target sequence of transmit vectors issued during an initial pass through the test program subsequent to the occurrence of the trigger. These addresses are exchanged for the instructions themselves, which are then altered to remove branching, and stored in a reserved portion of the memory they came from. Once the altered target sequence is stored the desired information is produced by restarting the entire test program and letting it run exactly as before down to the trigger. Now when the trigger occurs further transmit vectors are issued from the memorized target sequence, rather than from the live algorithm, and a combination of voltage thresholds and the sample timing offset are switched into place. After the target sequence the test program is re-started with normal thresholds and sample timing offsets. There is eventually another trigger, whereupon the memorized target sequence is again substituted while the next combination in the step along the acquisition sweep is instituted. This process is continued until the entire acquisition sweep has been performed. An inspection of the stored data allows creation of the waveforms.
摘要翻译： 内存测试仪的触发信号使用根据测试程序正在执行的部分进行限定的（断点）触发。 合格的断点触发可以在成为系统触发信号之前被延迟，该触发信号可用于触发“示波器模式”，并将错误标志强制到所选值，以便强制使用测试程序的特定路径。 为了提供用于扫描电压阈值和采样定时偏移的稳定波形，存储器测试器记录在触发发生之后在初始通过测试程序期间发出的发射矢量的目标序列的地址。 这些地址被交换为指令本身，然后改变它们以去除分支，并且存储在它们来自的存储器的保留部分中。 一旦存储了改变的目标序列，则通过重新启动整个测试程序并让其像以前那样精确地运行到触发器来产生所需的信息。 现在当触发发生时，从存储的目标序列而不是从实时算法发出发射矢量，并将电压阈值和采样定时偏移的组合切换到位。 在目标序列之后，测试程序以正常阈值和采样定时偏移重新启动。 最终有另一个触发器，随后记录的目标序列再次被替换，同时沿着采集扫描步骤中的下一个组合被建立。 此过程一直持续到整个采集扫描完成。 对存储的数据的检查允许创建波形。
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公开(公告)号：US06671844B1
公开(公告)日：2003-12-30
申请号：US09677202
申请日：2000-10-02
IPC分类号： G01R3128
CPC分类号： G11C29/56 , G11C2029/2602 , G11C2029/5606
摘要： A memory tester supports testing of multiple DUT's of the same type at a test site. The tester can be instructed to replicate the segments of the test vectors needed to test one DUT on the channels for the other DUT's. This produces patterns of transmit and receive vectors that are n-many DUT's wide. Conditional branching within the test program in response to conditions in the receive vectors (DUT failure) is supported by recognizing several types of error indications and an ability to selectively disable the testing of one or more DUT's while continuing to test the one or more that are not disabled. Also included are ways to remove or limit stimulus to particular DUT's, and ways to make all comparisons for a particular DUT appear to be “good.”
摘要翻译： 内存测试器支持在测试站点测试同一类型的多个DUT。 可以指示测试仪复制在另一个DUT的通道上测试一个DUT所需的测试矢量段。 这产生了多个DUT宽的发送和接收向量的模式。 通过识别几种类型的错误指示和选择性地禁用一个或多个DUT的测试，同时继续测试一个或多个DUT的能力，支持测试程序内响应于接收向量（DUT故障）条件的条件分支 没有禁用 还包括删除或限制对特定DUT的刺激的方法，并且对特定DUT进行所有比较的方法似乎是“好”。
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3.发明授权Method and apparatus for administering inversion property in a memory tester 有权用于在存储器测试器中管理反转特性的方法和装置公开(公告)号：US06973404B1
公开(公告)日：2005-12-06
申请号：US09659198
申请日：2000-09-11
IPC分类号： G01R31/28 , G01R31/319 , G11C29/00 , G11C29/56
CPC分类号： G01R31/31926 , G11C29/56
摘要： A method and apparatus permits use of a tester memory (31) as storage for an inversion mask. The inversion mask indicates to the tester which cells in a DUT memory (14) are logically inverted during testing. Data information and the inverse of the data information is input into a first data multiplexer (802). The stored inversion mask (902–908) is used to independently select a data information bit or its inverse for presentation as a masked output (814) at the output of the first data multiplexer (802).
摘要翻译： 方法和装置允许使用测试器存储器（31）作为反转掩模的存储。 反向掩模向测试者指示在测试期间DUT存储器（14）中的哪个单元在逻辑上反转。 数据信息和数据信息的反相被输入到第一数据多路复用器（802）中。 存储的反转掩模（902-908）用于在第一数据多路复用器（802）的输出处独立地选择数据信息位或其用于呈现的反向掩模作为屏蔽输出（814）。
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4.发明授权Method and apparatus for coordinating program execution in a site controller with pattern execution in a tester 失效用于在站点控制器中协调程序执行的方法和装置，其中在测试器中执行模式执行公开(公告)号：US06763490B1
公开(公告)日：2004-07-13
申请号：US09669262
申请日：2000-09-25
IPC分类号： G01R3128
CPC分类号： G11C29/56
摘要： A method and apparatus for coordinating program execution in a site controller with pattern execution in a tester executes the pattern in the tester and a pattern interruption instruction. The pattern interruption instruction causes the tester to write to a service request register in the site controller specifying a value that specifies a requested subroutine and a data source. The site controller initiates execution of the requested subroutine in the site controller using the specified data source.
摘要翻译： 用于协调位置控制器中的程序执行的方法和装置，其中在测试仪中执行模式执行，并执行模式中断指令。 模式中断指令使测试者写入站点控制器中的服务请求寄存器，指定指定所请求的子例程和数据源的值。 站点控制器使用指定的数据源启动站点控制器中所请求的子例程的执行。
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5.发明授权Method and apparatus for inserting programmable latency between address and data information in a memory tester 有权用于在存储器测试器中的地址和数据信息之间插入可编程等待时间的方法和装置公开(公告)号：US06591385B1
公开(公告)日：2003-07-08
申请号：US09659539
申请日：2000-09-11
IPC分类号： G11C2900
CPC分类号： G11C29/56012 , G11C29/56
摘要： A memory tester has a feature including a method and an apparatus, to programmably insert a latency between address and data channels. Address information is stored in a FIFO memory during a first program instruction cycle. After a desired number of program instruction cycles, the address information is retrieved during a second program instruction cycle. The retrieved address information is used to address a location in a tester memory for storage of data information received from a DUT. In this way, the data information is correlated to a latent address according to DUT specifications.
摘要翻译： 存储器测试器具有包括方法和装置的特征，可编程地在地址和数据信道之间插入等待时间。 地址信息在第一个程序指令周期中存储在FIFO存储器中。 在所需数量的程序指令周期之后，在第二程序指令周期期间检索地址信息。 检索到的地址信息用于寻址测试器存储器中用于存储从DUT接收的数据信息的位置。 以这种方式，根据DUT规格将数据信息与潜在地址相关联。
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6.发明授权公开(公告)号：US06748562B1
公开(公告)日：2004-06-08
申请号：US09702578
申请日：2000-10-31
IPC分类号： G11C2900
CPC分类号： G11C29/56
摘要： A test program generates transmit vectors (stimuli) and receive vectors (expected responses). The transmit vectors are applied to the DUT, while the receive vectors are treated as comparison values used to decide if a response from the DUT is as expected. While programming a FLASH part the test program uses TAG RAM techniques to maintain a BAD COLUMN table in one of the memory sets. This BAD COLUMN table is addressed by the same address that is applied to the DUT. If an OMIT BAD COLUMN mode is in effect, entries in this table are, by automatic action of the memory tester hardware, obtained and used to supply a replacement programming data value of all 1's that will produce an immediate and automatic indication of successful programming from the DUT. This prevents spending extra time programming a column that has been determined to be bad, without requiring an alteration in the internal mechanism of the test program. The discovery of bad columns and their recordation in the BAD COLUMN table can be performed during an initial programming phase of the test program, or it can be performed on an “as-discovered” basis during the course of exercising a programmed FLASH DUT. These features may be combined with automatic reading of a special BAD BLOCK table created in interior test memory to facilitate the testing of memory parts that have an internal block structure, by automatically disabling, and removing from further influence on the test program, actions related to a bad block. That bad block may or may not be in a DUT that is being tested in a multi-DUT fashion.
摘要翻译： 测试程序产生传输向量（刺激）和接收向量（预期响应）。 发射矢量被施加到DUT，而接收矢量被视为比较值，用于确定来自DUT的响应是否如预期的那样。 在编写FLASH部件时，测试程序使用TAG RAM技术在其中一个存储器集中维护一个BAD COLUMN表。 该BAD COLUMN表由应用于DUT的相同地址寻址。 如果OMIT BAD COLUMN模式有效，则表中的条目通过内存测试仪硬件的自动操作获取并用于提供所有1的替代编程数据值，该值将产生直接和自动指示成功编程 被测件。 这样可以避免花费额外的时间来编写已被确定为坏的列，而不需要更改测试程序的内部机制。 在BAD COLUMN表中发现不良列及其记录可以在测试程序的初始编程阶段执行，或者可以在运行编程的FLASH DUT的过程中以“发现”的方式执行。 这些特征可以与在内部测试存储器中创建的特殊BAD BLOCK表的自动读取相结合，以便于对具有内部块结构的存储器部件进行测试，通过自动禁用并消除对测试程序的进一步影响， 一个坏块 该坏块可能或可能不在以多DUT方式测试的DUT中。
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公开(公告)号：US06687855B1
公开(公告)日：2004-02-03
申请号：US09693218
申请日：2000-10-20
IPC分类号： G06F1126
CPC分类号： G06F11/26
摘要： An apparatus for automatically accumulating and storing information has a destination memory and an indexing circuit. The indexing circuit has an input port, a selector having a selector output, a register holding a value from the selector output and presenting the selector output value at a register output, and an accumulator accepting a value from the input port and a value from the register output and presenting a sum of the input port and register output values at an accumulator output. The selector receives the input port value from the input port, the accumulator output, and the value from the register output, the selector output being based upon a programmable selection code. The register output is connected to the destination memory .
摘要翻译： 用于自动存储和存储信息的装置具有目的地存储器和分度电路。 索引电路具有输入端口，具有选择器输出的选择器，保持来自选择器输出的值并在选择器输出端呈现选择器输出值的寄存器，以及从输入端口接收值的累加器和来自输入端口的值 寄存器输出，并在累加器输出端显示输入端口和寄存器输出值之和。 选择器从输入端口接收输入端口值，累加器输出和寄存器输出的值，选择器输出基于可编程选择代码。 寄存器输出连接到目标存储器。
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8.发明授权Algorithmically programmable memory tester with test sites operating in a slave mode 有权具有在从模式下运行的测试站点的算法可编程存储器测试器公开(公告)号：US06779140B2
公开(公告)日：2004-08-17
申请号：US09896474
申请日：2001-06-29
IPC分类号： G11C2900
CPC分类号： G11C29/56 , G01R31/31907
摘要： A Test Station for a memory tester is comprised of one or more Test Sites that are each individually algorithmically controllable, that can each deal with as many as sixty-four channels, and that can be bonded together to form a Multi-Site Test Station of two or more Test Sites. Up to nine Test Sites can be bonded together as a single Multi-Site Test Station. Bonded Test Sites still operate at the highest speeds they were capable of when not bonded. To bring this about it is necessary to implement certain programming conventions and to provide certain housekeeping functions relating to simultaneous starting of separate test programs on the bonded Test Sites, and relating to propagation and synchronization of test program qualifier results among those separate test programs. There also is a suspend/resume test program execution mechanism that assists one test program in temporarily interrupting the others to allow time for a change within one or more of the Test Sites of a measurement parameter, such as a voltage comparison threshold.
摘要翻译： 用于记忆测试仪的测试站由一个或多个测试站组成，每个测试站点各自具有算术可控性，每个测试站点可以处理多达六十四个通道，并且可以结合在一起以形成多站点测试站 两个或多个测试站点。 多达9个测试站点可以作为单个多站点测试站绑定在一起。 保税测试站点仍然以最高的速度运行，当他们没有绑定时能够实现。 为了实现这一点，有必要实施某些编程约定，并提供与在绑定的测试站点上单独测试程序同时启动有关的某些内务管理功能，以及与单独的测试程序之间的测试程序限定符结果的传播和同步有关。 还有一个暂停/恢复测试程序执行机制，协助一个测试程序临时中断其他测试程序，以便在测量参数的一个或多个测试站点内进行更改，例如电压比较阈值。
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9.发明授权Memory tester uses arbitrary dynamic mappings to serialize vectors into transmitted sub-vectors and de-serialize received sub-vectors into vectors 有权存储器测试仪使用任意的动态映射将矢量序列化为传输的子向量，并将接收的子向量序列化为向量公开(公告)号：US07076714B2
公开(公告)日：2006-07-11
申请号：US10683796
申请日：2003-10-10
申请人： John H Cook, III , Alan S Krech, Jr. , Stephen D Jordan , Edmundo De La Puente , John M Freesman
发明人： John H Cook, III , Alan S Krech, Jr. , Stephen D Jordan , Edmundo De La Puente , John M Freesman
CPC分类号： G11C29/56004 , G11C16/04 , G11C29/56
摘要： The problem of sequentially “squeezing” small fields of data in a larger data path in and out of a memory device can be solved in an algorithmically driven memory tester by defining sub-vectors to represent data in the small field, where a sequence of sub-vectors represents the data that would be represented by a full sized vector if such a full sized vector could be applied to the DUT. A programming construct in the programming language of the algorithmically driven memory tester allows sub-vectors to be defined, as well as an arbitrary mapping that each is to have. The arbitrary mapping is not static, but changes dynamically as different sub-vectors are encountered. Arbitrary dynamic mappings change as sub-vectors are processed, and may include the notion that, during the activity for a sub-vector, this (or these) bit(s) of a vector do not (presently) map to any pin at all of the DUT. The arbitrary dynamic mapping is implemented by a collection of MUX's configured by data stored ahead of time in an SRAM, in accordance with what defining program constructs are encountered by the compiler as it processes the test program. A dynamic reverse mapper, also a collection of MUX's similarly controlled by an SRAM, serves as a de-serializer that assembles a sequence of received sub-vectors into a final received full-sized vector.
摘要翻译： 可以在算法驱动的存储器测试器中通过定义子向量来表示小字段中的数据来解决在存储器件中的较大数据路径中顺序地“挤压”小数据数据的问题，其中子序列 - 如果这样的全尺寸向量可以应用于DUT，则向量表示将由全尺寸向量表示的数据。 算法驱动的内存测试器的编程语言中的编程结构允许定义子向量，以及每个都具有的任意映射。 任意映射不是静态的，但是随着不同的子向量遇到动态变化。 任意动态映射随着子向量被处理而改变，并且可以包括在子向量的活动期间，向量的（或这些）比特（目前）不会（至少）映射到任何引脚的概念 的DUT。 根据编译器在处理测试程序时遇到的定义程序构造的任何动态映射由通过SRAM中提前存储的数据配置的MUX集合来实现。 动态反向映射器，也是由SRAM类似地控制的MUX的集合，用作解串器，其将接收的子向量的序列组装成最终接收的全尺寸向量。
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10.发明授权Method and apparatus for executing a program using primary, secondary and tertiary memories 有权使用主，次和三级存储器执行程序的方法和装置公开(公告)号：US06598112B1
公开(公告)日：2003-07-22
申请号：US09659259
申请日：2000-09-11
IPC分类号： G06F1200
摘要： A method and apparatus for executing an integrated circuit (IC) test program including at least one calling instruction partitions at least one called subroutine into first and second subroutine portions, loads IC test program instructions into a primary memory, loads the first subroutine portion into the primary memory contiguous with the calling instruction, inserts a memory transfer access instruction after the first portion, and loads a remainder of the IC test program instructions into primary memory. The method then executes instructions from primary memory. Execution of the calling instruction in the primary memory causes the second subroutine portion to be loaded into a FIFO element from a secondary memory. The first subroutine portion executes from the primary memory. Execution of the memory transfer access instruction initiates fetching and executing the second portion of the called subroutine from a first-in-first-out (FIFO) element.
摘要翻译： 一种用于执行集成电路（IC）测试程序的方法和装置，包括至少一个调用指令，将至少一个被称为子程序的分区分成第一和第二子程序部分，将IC测试程序指令加载到主存储器中，将第一子程序部分加载到 与调用指令相邻的主存储器在第一部分之后插入存储器传送访问指令，并将其余的IC测试程序指令加载到主存储器中。 该方法然后从主存储器执行指令。 在主存储器中执行调用指令使第二子程序部分从辅助存储器加载到FIFO元素中。 第一个子程序部分从主存储器执行。 存储器传送访问指令的执行启动从先进先出（FIFO）元素获取和执行被调用子程序的第二部分。
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