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    PERFORMANCE INVERSION DETECTION CIRCUIT AND A DESIGN STRUCTURE FOR THE SAME
    1.
    发明申请
    PERFORMANCE INVERSION DETECTION CIRCUIT AND A DESIGN STRUCTURE FOR THE SAME 审中-公开
    性能反相检测电路及其设计结构

    公开(公告)号：US20090179670A1

    公开(公告)日：2009-07-16

    申请号：US12014430

    申请日：2008-01-15

    申请人： Albert M. Chu ,  John A. Fifield ,  Daryl M. Seitzer ,  Hongfei Wu

    发明人： Albert M. Chu ,  John A. Fifield ,  Daryl M. Seitzer ,  Hongfei Wu

    IPC分类号： H03F3/45

    CPC分类号： H03F3/45475 ,  H03F2200/447 ,  H03F2203/45586 ,  H03F2203/45618 ,  H03F2203/45622

    摘要： A circuit containing a parallel connection of a first sub-circuit and a second sub-circuit is provided. The first sub-circuit comprises a serial connection of a first field effect transistor having a first threshold voltage and a first voltage dividing device. The second sub-circuit comprises a serial connection of a second field effect transistor having a second threshold voltage, which is different from the first threshold voltage, and a second voltage dividing device. The voltage between the first field effect transistor and the first voltage dividing device is compared with the voltage between the second field effect transistor and the second voltage dividing device so that a signal may be generated at a temperature at which the ratio of a performance parameter such as on-current between the first and second field effect transistors crosses over a predefined value. The signal may be advantageously employed to actively control circuit characteristics.

    摘要翻译： 提供了包含第一子电路和第二子电路的并联连接的电路。 第一子电路包括具有第一阈值电压的第一场效应晶体管和第一分压装置的串联连接。 第二子电路包括具有与第一阈值电压不同的第二阈值电压的第二场效应晶体管的串联连接和第二分压装置。 将第一场效应晶体管和第一分压装置之间的电压与第二场效应晶体管和第二分压装置之间的电压进行比较，使得可以在这样的温度下产生信号， 因为第一和第二场效应晶体管之间的导通电流跨越预定值。 可以有利地使用该信号来主动地控制电路特性。

    Voltage Detection Circuit in an Integrated Circuit and Method of Generating a Trigger Flag Signal
    6.
    发明申请
    Voltage Detection Circuit in an Integrated Circuit and Method of Generating a Trigger Flag Signal 有权
    集成电路中的电压检测电路和产生触发标志信号的方法

    公开(公告)号：US20090021289A1

    公开(公告)日：2009-01-22

    申请号：US12242114

    申请日：2008-09-30

    申请人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  Albert M. Chu ,  John A. Fifield

    发明人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  Albert M. Chu ,  John A. Fifield

    IPC分类号： H03L7/00

    CPC分类号： H03K5/153

    摘要： An integrated circuit that includes at least one tunneling device voltage detection circuit for generating a trigger flag signal. The tunneling device voltage detection circuit includes first and second voltage dividers receiving a supply voltage and having corresponding respective first and second internal node output voltages. The first and second voltage dividers are configured so the first output voltage is linear relative to the supply voltage and so that the second output voltage is nonlinear relative to the supply voltage. As the supply voltage ramps up, the profiles of the first and second output voltage cross at a particular voltage. An operational amplifier circuit senses when the first and second output voltages become equal and, in response thereto, outputs a trigger signal that indicates that the supply voltage has reached a certain level.

    摘要翻译： 一种集成电路，其包括用于产生触发标志信号的至少一个隧道装置电压检测电路。 隧道装置电压检测电路包括接收电源电压并具有对应的相应的第一和第二内部节点输出电压的第一和第二分压器。 第一和第二分压器被配置为使得第一输出电压相对于电源电压是线性的，并且使得第二输出电压相对于电源电压是非线性的。 随着电源电压上升，第一和第二输出电压的曲线在特定电压下交叉。 运算放大器电路检测第一和第二输出电压何时相等，并且响应于此，输出指示电源电压达到一定水平的触发信号。

    Digital delay line with low insertion delay
    7.
    发明授权
    Digital delay line with low insertion delay 失效
    具有低插入延迟的数字延迟线

    公开(公告)号：US06285229B1

    公开(公告)日：2001-09-04

    申请号：US09471898

    申请日：1999-12-23

    申请人： Albert M. Chu ,  Frank D. Ferraiolo ,  John A. Fifield ,  Teresa Thi Nguyen ,  Michael Sofranko

    发明人： Albert M. Chu ,  Frank D. Ferraiolo ,  John A. Fifield ,  Teresa Thi Nguyen ,  Michael Sofranko

    IPC分类号： H03H1126

    CPC分类号： H03K5/131 ,  H03K5/133 ,  H03K2005/00058

    摘要： A variable digital delay line with an insertion delay as low as a single delay element yet capable of providing a large programmable delay with a small simple control mechanism. A loop connects an input to an output through selectable first delay elements such as 2:1 muxes and selectable second delay elements such as pairs of inverters by way of a plurality of intermediate nodes having a tap. A plurality of sneak paths are available wherein the loop by passes a remainder of first delay elements and/or second delay elements by way of the taps at the intermediate nodes.

    摘要翻译： 一种可变数字延迟线，其插入延迟低至单个延迟元件，但能够利用小的简单控制机制提供大的可编程延迟。 环路通过可选择的第一延迟元件（例如2：1多路复用器）和可选择的第二延迟元件（例如成对的反相器）通过具有抽头的多个中间节点将输入连接到输出。 多个潜行路径是可用的，其中循环通过中间节点处的抽头通过第一延迟元件的剩余部分和/或第二延迟元件。

    Delay-locked-loop (DLL) having symmetrical rising and falling clock edge type delays
    8.
    发明授权
    Delay-locked-loop (DLL) having symmetrical rising and falling clock edge type delays 有权
    具有对称的上升和下降时钟边缘类型延迟的延迟锁定环（DLL）

    公开(公告)号：US6127866A

    公开(公告)日：2000-10-03

    申请号：US239487

    申请日：1999-01-28

    申请人： Albert M. Chu ,  John A. Fifield ,  Jason E. Rotella ,  Jean-Marc Dortu

    发明人： Albert M. Chu ,  John A. Fifield ,  Jason E. Rotella ,  Jean-Marc Dortu

    IPC分类号： H03K5/15 ,  G11C7/22 ,  H03L7/081 ,  H03L7/095 ,  H03L7/06

    CPC分类号： H03L7/0814 ,  G11C7/22 ,  H03L7/095

    摘要： A circuit and method are provided wherein a receiver receives an input train of pulses. The circuit includes a delay-locked-loop coupled to an output of the receiver. The delay-locked-loop includes a pulse generator responsive to received input train of pulses produced at the output of the receiver for producing first pulses in response to the leading edges of the received input train of pulses and second pulses in response to the trailing edges of received input train of pulses. The leading edge of the first pulse has the same edge type as the leading edge of the second pulse (i.e., the leading edge of the first pulse and the leading edge of the second pulse are either both rising edge types or both falling edges types). The first pulses and the second pulses are combined into a composite input signal comprising the first and second pulses with the leading edge of the first pulse maintaining the same edge type. The delay-locked-loop also includes a variable delay line fed by the composite input signal for producing a composite output train of pulses comprising both the first train of pulses and the second train of pulses after a selected time delay provided by the delay line. The delay-locked-loop is responsive to one of the first train of pulses and the second train of pulses in the composite output train of pulses for selecting the time delay of the variable delay line so as to produce the composite output train of pulses with a predetermined phase relationship to the input train of pulses.

    摘要翻译： 提供一种电路和方法，其中接收器接收输入的脉冲序列。 电路包括耦合到接收器的输出的延迟锁定环路。 延迟锁定环包括响应于在接收器的输出处产生的接收到的输入脉冲序列的脉冲发生器，以响应于所接收的输入脉冲序列的前沿和响应于后沿的第二脉冲而产生第一脉冲 的接收输入脉冲序列。 第一脉冲的前沿具有与第二脉冲的前沿相同的边缘类型（即，第一脉冲的前沿和第二脉冲的前沿都是上升沿类型或两个下降沿类型） 。 第一脉冲和第二脉冲被组合成包括第一和第二脉冲的复合输入信号，其中第一脉冲的前沿保持相同的边缘类型。 延迟锁定环还包括由复合输入信号馈送的可变延迟线，用于在由延迟线提供的选定时间延迟之后产生包括第一脉冲串和第二脉冲串的两个脉冲的复合输出串。 延迟锁定回路响应于复合输出脉冲串中的第一脉冲序列和第二脉冲串中的一个，用于选择可变延迟线的时间延迟，以便产生具有 与输入的脉冲序列的预定相位关系。

    Structure for a voltage detection circuit in an integrated circuit and method of generating a trigger flag signal
    9.
    发明授权
    Structure for a voltage detection circuit in an integrated circuit and method of generating a trigger flag signal 有权
    集成电路中的电压检测电路的结构和产生触发标志信号的方法

    公开(公告)号：US07873921B2

    公开(公告)日：2011-01-18

    申请号：US11948308

    申请日：2007-11-30

    申请人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  Albert M. Chu ,  John A. Fifield

    发明人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  Albert M. Chu ,  John A. Fifield

    IPC分类号： G06F17/50 ,  H03L7/00

    CPC分类号： G06F17/5063 ,  G06F2217/78

    摘要： A design structure for an integrated circuit that includes at least one tunneling device voltage detection circuit for generating a trigger flag signal. The tunneling device voltage detection circuit includes first and second voltage dividers receiving a supply voltage and having corresponding respective first and second internal node output voltages. The first and second voltage dividers are configured so the first output voltage is linear relative to the supply voltage and so that the second output voltage is nonlinear relative to the supply voltage. As the supply voltage ramps up, the profiles of the first and second output voltage cross at a particular voltage. An operational amplifier circuit senses when the first and second output voltages become equal and, in response thereto, outputs a trigger signal that indicates that the supply voltage has reached a certain level.

    摘要翻译： 一种用于集成电路的设计结构，其包括用于产生触发标志信号的至少一个隧道装置电压检测电路。 隧道装置电压检测电路包括接收电源电压并具有对应的相应的第一和第二内部节点输出电压的第一和第二分压器。 第一和第二分压器被配置为使得第一输出电压相对于电源电压是线性的，并且使得第二输出电压相对于电源电压是非线性的。 随着电源电压上升，第一和第二输出电压的曲线在特定电压下交叉。 运算放大器电路检测第一和第二输出电压何时相等，并且响应于此，输出指示电源电压达到一定水平的触发信号。

    Voltage detection circuit in an integrated circuit and method of generating a trigger flag signal
    10.
    发明授权
    Voltage detection circuit in an integrated circuit and method of generating a trigger flag signal 有权
    集成电路中的电压检测电路和产生触发标志信号的方法

    公开(公告)号：US07847605B2

    公开(公告)日：2010-12-07

    申请号：US12242114

    申请日：2008-09-30

    申请人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  Albert M. Chu ,  John A. Fifield

    发明人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  Albert M. Chu ,  John A. Fifield

    IPC分类号： H03L7/00

    CPC分类号： H03K5/153

    摘要： An integrated circuit that includes at least one tunneling device voltage detection circuit for generating a trigger flag signal. The tunneling device voltage detection circuit includes first and second voltage dividers receiving a supply voltage and having corresponding respective first and second internal node output voltages. The first and second voltage dividers are configured so the first output voltage is linear relative to the supply voltage and so that the second output voltage is nonlinear relative to the supply voltage. As the supply voltage ramps up, the profiles of the first and second output voltage cross at a particular voltage. An operational amplifier circuit senses when the first and second output voltages become equal and, in response thereto, outputs a trigger signal that indicates that the supply voltage has reached a certain level.

    摘要翻译： 一种集成电路，其包括用于产生触发标志信号的至少一个隧道装置电压检测电路。 隧道装置电压检测电路包括接收电源电压并具有对应的相应的第一和第二内部节点输出电压的第一和第二分压器。 第一和第二分压器被配置为使得第一输出电压相对于电源电压是线性的，并且使得第二输出电压相对于电源电压是非线性的。 随着电源电压上升，第一和第二输出电压的曲线在特定电压下交叉。 运算放大器电路检测第一和第二输出电压何时相等，并且响应于此，输出指示电源电压达到一定水平的触发信号。