公开(公告)号：US20080001295A1

公开(公告)日：2008-01-03

申请号：US11855229

申请日：2007-09-14

Applicant: Simone Alba ,  Alessandro Spandre ,  Barbara Zanderighi

Inventor： Simone Alba ,  Alessandro Spandre ,  Barbara Zanderighi

IPC: H01L23/48

CPC classification number: H01L21/76838 ,  H01L21/0332 ,  H01L21/32139 ,  H01L21/76834

Abstract: The method prevents oxidation or contamination phenomena of conductive interconnection structures in semiconductor devices and includes providing a layer of semiconductor or oxide base, a conductive layer or stack on the base layer, and an antireflection coating (ARC) layer on the conductive layer or stack. The method provides a thin dielectric covering layer on the antireflection coating layer to fill or cover the microfissures existing in the antireflection coating layer.

Abstract translation: 该方法防止半导体器件中的导电互连结构的氧化或污染现象，并且包括在基底层上提供半导体层或氧化物层，导电层或叠层，以及导电层或叠层上的抗反射涂层（ARC）层。 该方法在抗反射涂层上提供薄的电介质覆盖层，以填充或覆盖存在于抗反射涂层中的微裂缝。

公开(公告)号：US07256130B2

公开(公告)日：2007-08-14

申请号：US10837491

申请日：2004-04-30

Applicant: Alessandro Spandre

Inventor： Alessandro Spandre

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L45/1233 ,  C23F4/00 ,  H01L45/06 ,  H01L45/144 ,  H01L45/1675

Abstract: A process for defining a chalcogenide material layer using a chlorine based plasma and a mask, wherein the portions of the chalcogenide material layer that are not covered by the mask are etched away. In a phase change memory cell having a stack of a chalcogenide material layer and an AlCu layer, the AlCu layer is etched first using a chlorine based plasma at a higher temperature; then the lateral walls of the AlCu layer are passivated; and then the chalcogenide material layer is etched at a lower temperature.

Abstract translation: 使用氯基等离子体和掩模来限定硫族化物材料层的方法，其中未被掩模覆盖的硫属化物材料层的部分被蚀刻掉。 在具有硫族化物材料层和AlCu层的堆叠的相变存储单元中，首先使用氯系等离子体在较高温度下蚀刻AlCu层; 那么AlCu层的侧壁被钝化; 然后在较低温度下蚀刻硫族化物材料层。

公开(公告)号：US20050142863A1

公开(公告)日：2005-06-30

申请号：US11018213

申请日：2004-12-20

Applicant: Alessandro Spandre

Inventor： Alessandro Spandre

IPC: H01L21/311 ,  H01L21/768 ,  H01L45/00 ,  H01L21/76 ,  H01L21/4763

CPC classification number: H01L21/31116 ,  H01L21/76804 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

Abstract: A process for forming a tapered trench in a dielectric material includes the steps of forming a dielectric layer on a semiconductor wafer, and plasma etching the dielectric layer; during the plasma etch, the dielectric layer is chemically and physically etched simultaneously.

Abstract translation: 在电介质材料中形成锥形沟槽的工艺包括以下步骤：在半导体晶片上形成电介质层，等离子体蚀刻电介质层; 在等离子体蚀刻期间，电介质层被化学和物理同时蚀刻。

公开(公告)号：US07247573B2

公开(公告)日：2007-07-24

申请号：US11018213

申请日：2004-12-20

Applicant: Alessandro Spandre

Inventor： Alessandro Spandre

IPC: H01L21/302

CPC classification number: H01L21/31116 ,  H01L21/76804 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

Abstract: A process for forming a tapered trench in a dielectric material includes the steps of forming a dielectric layer on a semiconductor wafer, and plasma etching the dielectric layer; during the plasma etch, the dielectric layer is chemically and physically etched simultaneously.

Abstract translation: 在电介质材料中形成锥形沟槽的工艺包括以下步骤：在半导体晶片上形成电介质层，等离子体蚀刻电介质层; 在等离子体蚀刻期间，电介质层被化学和物理同时蚀刻。

公开(公告)号：US20060261036A1

公开(公告)日：2006-11-23

申请号：US11401113

申请日：2006-04-10

Applicant: Giuseppe Fazio ,  Alessandro Spandre ,  Pietro Petruzza

Inventor： Giuseppe Fazio ,  Alessandro Spandre ,  Pietro Petruzza

IPC: G01L21/30 ,  H01L21/302 ,  C23F1/00 ,  B44C1/22

CPC classification number: H01L21/31116

Abstract: A method is provided for patterning a wafer comprising at least one substrate for the manufacture of an integrated circuit. The method comprises: etching at least one portion of the substrate with a reactive gas plasma to obtain an optical emission signal, resulting from the products of the reaction between the plasma and the substrate and having a predetermined spectral fingerprint; carrying on the etching of the substrate up to a predetermined end point; and monitoring the spectral fingerprint of the optical emission signal to detect the etching end point. The method comprises the further insertion of an inert gas in the plasma to obtain an increase in the intensity of the optical emission signal.

Abstract translation: 提供了一种用于图案化包括至少一个用于制造集成电路的衬底的晶片的方法。 该方法包括：用反应气体等离子体蚀刻衬底的至少一部分，以获得由等离子体和衬底之间的反应产物产生并具有预定光谱指纹的光发射信号; 进行基板的蚀刻直到预定的端点; 并监测光发射信号的光谱指纹，以检测蚀刻终点。 该方法包括在等离子体中进一步插入惰性气体以获得光发射信号强度的增加。

公开(公告)号：US07288427B2

公开(公告)日：2007-10-30

申请号：US11009687

申请日：2004-12-10

Applicant: Simone Alba ,  Alessandro Spandre ,  Barbara Zanderighi

Inventor： Simone Alba ,  Alessandro Spandre ,  Barbara Zanderighi

IPC: H01L21/00

CPC classification number: H01L21/76801 ,  H01L21/0332 ,  H01L21/32139 ,  H01L21/76834 ,  H01L21/76838

Abstract: The method prevents oxidation or contamination phenomena of conductive interconnection structures in semiconductor devices and includes providing a layer of semiconductor or oxide base, a conductive layer or stack on the base layer, and an antireflection coating (ARC) layer on the conductive layer or stack. The method provides a thin dielectric covering layer on the antireflection coating layer to fill or cover the microfissures existing in the antireflection coating layer.

Abstract translation: 该方法防止半导体器件中的导电互连结构的氧化或污染现象，并且包括在基底层上提供半导体层或氧化物层，导电层或叠层，以及导电层或叠层上的抗反射涂层（ARC）层。 该方法在抗反射涂层上提供薄的电介质覆盖层，以填充或覆盖存在于抗反射涂层中的微裂缝。

公开(公告)号：US20050186780A1

公开(公告)日：2005-08-25

申请号：US11009687

申请日：2004-12-10

Applicant: Simone Alba ,  Alessandro Spandre ,  Barbara Zanderighi

Inventor： Simone Alba ,  Alessandro Spandre ,  Barbara Zanderighi

IPC: H01L21/033 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/44 ,  H01L21/768

CPC classification number: H01L21/76801 ,  H01L21/0332 ,  H01L21/32139 ,  H01L21/76834 ,  H01L21/76838

Abstract: The method prevents oxidation or contamination phenomena of conductive interconnection structures in semiconductor devices and includes providing a layer of semiconductor or oxide base, a conductive layer or stack on the base layer, and an antireflection coating (ARC) layer on the conductive layer or stack. The method provides a thin dielectric covering layer on the antireflection coating layer to fill or cover the microfissures existing in the antireflection coating layer.

Abstract translation: 该方法防止半导体器件中的导电互连结构的氧化或污染现象，并且包括在基底层上提供半导体层或氧化物层，导电层或叠层，以及导电层或叠层上的抗反射涂层（ARC）层。 该方法在抗反射涂层上提供薄的电介质覆盖层，以填充或覆盖存在于抗反射涂层中的微裂缝。

公开(公告)号：US20050032374A1

公开(公告)日：2005-02-10

申请号：US10837491

申请日：2004-04-30

Applicant: Alessandro Spandre

Inventor： Alessandro Spandre

IPC: C23F4/00 ,  H01L45/00 ,  H01L21/302 ,  H01L21/461

CPC classification number: H01L45/1233 ,  C23F4/00 ,  H01L45/06 ,  H01L45/144 ,  H01L45/1675

Abstract: A process for defining a chalcogenide material layer using a chlorine based plasma and a mask, wherein the portions of the chalcogenide material layer that are not covered by the mask are etched away. In a phase change memory cell having a stack of a chalcogenide material layer and an AlCu layer, the AlCu layer is etched first using a chlorine based plasma at a higher temperature; then the lateral walls of the AlCu layer are passivated; and then the chalcogenide material layer is etched at a lower temperature.

Abstract translation: 使用氯基等离子体和掩模来限定硫族化物材料层的方法，其中未被掩模覆盖的硫属化物材料层的部分被蚀刻掉。 在具有硫族化物材料层和AlCu层的堆叠的相变存储单元中，首先使用氯系等离子体在较高温度下蚀刻AlCu层; 那么AlCu层的侧壁被钝化; 然后在较低温度下蚀刻硫族化物材料层。