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    Clock recovery apparatus including a clock frequency adjuster
    3.
    发明授权
    Clock recovery apparatus including a clock frequency adjuster 失效
    时钟恢复装置，包括时钟频率调节器

    公开(公告)号：US4959846A

    公开(公告)日：1990-09-25

    申请号：US405806

    申请日：1989-09-11

    申请人： William R. Apple ,  William R. Freeman ,  Paulmer M. Soderberg ,  Lyle Thompson ,  Mark S. Thomas

    发明人： William R. Apple ,  William R. Freeman ,  Paulmer M. Soderberg ,  Lyle Thompson ,  Mark S. Thomas

    IPC分类号： H04L7/033 ,  H04L7/04

    CPC分类号： H04L7/0338 ,  H04L7/044

    摘要： A digital phase acquisition circuit includes circuits for detecting an edge of incoming data and a plurality of candidate clock phases, the circuitry further including logic for determining when the data undergoes a predetermined phase transition and at least one candidate phase which undergoes a digitally equivalent transition close in time to the data transition so as to enable the candidate phase to be used for choosing an appropriate clock phase for recovering information representative of the data. The circuit further includes logic for comparing a frequency of the chosen clock pulse and the data and adjusting at least one of these frequencies when a predetermined amount of drift therebetween is detected. The invention allows clock to be recovered within 1 bit time of a predetermined data transition occurring and allows an appropriate clock to be maintained through an entire packet regardless of packet length.

    摘要翻译： 数字相位获取电路包括用于检测输入数据和多个候选时钟相位的边缘的电路，该电路还包括用于确定数据何时经历预定相位转移的逻辑和经历数字等效转换关闭的至少一个候选相位 在时间上进行数据转换，以便使候选阶段能够用于选择用于恢复表示数据的信息的适当的时钟相位。 电路还包括用于比较所选择的时钟脉冲和数据的频率并在检测到预定量的漂移之间时调整这些频率中的至少一个的逻辑。 本发明允许在发生预定数据转换的1位时间内恢复时钟，并允许通过整个分组维持适当的时钟，而不管分组长度如何。

    Digital phase acquisition with delay locked loop
    4.
    发明授权
    Digital phase acquisition with delay locked loop 失效
    带延迟锁定环路的数字相位采集

    公开(公告)号：US6044122A

    公开(公告)日：2000-03-28

    申请号：US787849

    申请日：1997-01-23

    申请人： William F. Ellersick ,  William L. Geller ,  Paulmer M. Soderberg

    发明人： William F. Ellersick ,  William L. Geller ,  Paulmer M. Soderberg

    IPC分类号： H04L7/033 ,  H04L7/04 ,  H04L7/02

    CPC分类号： H04L7/0338 ,  H04L7/046

    摘要： A digital phase acquisition clock recovery circuit includes a digital phase-locked loop that employs a truth table decoder to set the actual delay through a plurality of individual delay elements to generate a plurality of clock phase signals approximately equally spaced in time over one reference clock cycle, and a data sampler circuit that generates a plurality of received data samples from an incoming data sample taken at the rising edge of the respective clock phase signals and synchronizes the data samples to reference clock on a bit period-by-bit period basis. A digital phase acquisition circuit includes an edge detector which evaluates the data samples over each bit period to detect the location of a transition between respective adjacent samples, wherein logic is employed to continually determine the "relative quality" of each data sample, based upon its sampling time being furthest from a detected edge transition. The data sample phase associated with the highest relative quality value integrated over time is then used to recover the incoming (i.e., optimally phased) data signal.

    摘要翻译： 数字相位采集时钟恢复电路包括数字锁相环，其采用真值表解码器来设置通过多个单独的延迟元件的实际延迟，以在一个参考时钟周期上产生大致相等时间间隔的时钟相位信号 以及数据采样器电路，其从在各个时钟相位信号的上升沿获取的输入数据样本产生多个接收数据样本，并且以比特周期为基础将数据采样同步到参考时钟。 数字相位获取电路包括边缘检测器，其对每个位周期的数据样本进行评估，以检测各个相邻采样之间的转换位置，其中采用逻辑来连续地确定每个数据采样的“相对质量” 采样时间距离检测到的边沿过渡最远。 然后使用与随时间积分的最高相对质量值相关联的数据采样阶段来恢复输入（即，最佳相位）数据信号。

    Clock recovery apparatus
    5.
    发明授权
    Clock recovery apparatus 失效
    时钟恢复装置

    公开(公告)号：US4975929A

    公开(公告)日：1990-12-04

    申请号：US405799

    申请日：1989-09-11

    申请人： William R. Apple ,  William R. Freeman ,  Paulmer M. Soderberg

    发明人： William R. Apple ,  William R. Freeman ,  Paulmer M. Soderberg

    IPC分类号： H04L7/033 ,  H04L7/04

    CPC分类号： H04L7/0338 ,  H04L7/044

    摘要： A digital phase acquisition circuit includes logic for detecting an edge of incoming data and a plurality of candidate clock phases, the circuitry further including logic for determining when the data undergoes a phase transition and at least one candidate phase which undergoes a digitally equivalent transition close in time to the data transition so as to enable the candidate phase to be used for a clock for recovering information representative of the data. The circuit allows clock to be recovered within 1 bit time of a predetermined data transition occurring, thus allowing preambles of 1 bit to be utilized in data packets.

    摘要翻译： 数字相位获取电路包括用于检测输入数据和多个候选时钟相位的边缘的逻辑，该电路还包括用于确定数据何时经历相变的逻辑和经历数字等效转换的至少一个候选相位 时间到数据转换，以使候选阶段能够用于恢复表示数据的信息的时钟。 电路允许在发生预定数据转换的1位时间内恢复时钟，从而允许在数据分组中使用1比特的前导码。

    Coupler verification test circuit
    6.
    发明授权
    Coupler verification test circuit 失效
    耦合器验证测试电路

    公开(公告)号：US5066139A

    公开(公告)日：1991-11-19

    申请号：US399686

    申请日：1989-08-28

    申请人： Paulmer M. Soderberg ,  Kristin K. Foss ,  Thomas E. Giles ,  Ralph A. Narciso

    发明人： Paulmer M. Soderberg ,  Kristin K. Foss ,  Thomas E. Giles ,  Ralph A. Narciso

    IPC分类号： H04B3/46 ,  H04B10/08

    CPC分类号： H04B10/07

    摘要： A coupler verification test circuit includes first and second circuits one of which is disposed at a head end of an optical fiber network and the other of which is disposed at a subscriber interface unit to be attached to the network when the head end is not operational. The subscriber interface circuit transmits instructions to a transceiver board in the subscriber interface unit for transmission to the network head end whereat the circuit thereat generates either no return signal, an acknowledgment return signal, or a default return signal. The test circuit at the subscriber interface unit then analyzes the return signal and visually indicates to a craftsman whether or not the transceiver board and other components of the SIU are operating correctly, e.g. whether or not the acknowledgement signal was returned and detected.

    摘要翻译： 耦合器验证测试电路包括第一和第二电路，其中之一设置在光纤网络的头端，另一个电路设置在用户接口单元，以便在头端不可操作时附接到网络。 用户接口电路向用户接口单元中的收发器板发送指令以传输到网络头端，其中电路不产生返回信号，确认返回信号或默认返回信号。 用户接口单元上的测试电路然后分析返回信号，并向工匠直观地指示收发器板和SIU的其他部件是否正常工作，例如， 是否返回并检测到确认信号。